公开(公告)号：US11082048B1

公开(公告)日：2021-08-03

申请号：US17017446

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Yuji Satoh ,  Mitsuyuki Ashida

IPC: H03L7/08 ,  H03L7/081 ,  H03K7/08 ,  H03L7/18 ,  H03L7/183

Abstract: According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

公开(公告)号：US11894095B2

公开(公告)日：2024-02-06

申请号：US17685230

申请日：2022-03-02

Applicant: KIOXIA CORPORATION

Inventor： Yuji Satoh ,  Hiromitsu Komai

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1087

Abstract: A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.

公开(公告)号：US11303290B2

公开(公告)日：2022-04-12

申请号：US17004224

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Yuji Satoh

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/12 ,  H03M1/10

Abstract: In a semiconductor integrated circuit, a first generation circuit generates a common mode voltage of a differential signal. A second generation circuit generates temperature information according to the common mode voltage. The temperature information is information corresponding to a characteristic of an amplifier circuit related to an ambient temperature. A correction circuit corrects a first reference voltage and a second reference voltage according to the temperature information. A comparator includes a first input node to which a first signal line is electrically connected; a second input node to which a second signal line is electrically connected; a third input node to which the corrected first reference voltage is input; and a fourth input node to which the corrected second reference voltage is input.