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公开(公告)号：US11783899B2
公开(公告)日：2023-10-10
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
CPC classification number: G11C16/14 , G11C16/26 , G11C16/30 , G11C16/3445
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US11410974B2
公开(公告)日：2022-08-09
申请号：US17011487
申请日：2020-09-03
Applicant: KIOXIA CORPORATION
Inventor： Masahiro Yoshihara , Toshikazu Watanabe , Nobuharu Miyata , Yasumitsu Nozawa , Tomohito Kawano , Sachie Fukuda , Akiyoshi Itou , Toshimitsu Iwasawa
Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.
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公开(公告)号：US11532363B2
公开(公告)日：2022-12-20
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US11417401B2
公开(公告)日：2022-08-16
申请号：US17008209
申请日：2020-08-31
Applicant: KIOXIA CORPORATION
Inventor： Mario Sako , Hiromitsu Komai , Masahiro Yoshihara
IPC: G11C16/26 , H01L23/522 , G11C16/04 , G11C16/10 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L27/11556
Abstract: A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.
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Patent Agency Ranking
公开(公告)号：US11270981B2
公开(公告)日：2022-03-08
申请号：US17023617
申请日：2020-09-17
Applicant: KIOXIA CORPORATION
Inventor： Mikihiko Ito , Masaru Koyanagi , Masafumi Nakatani , Shinya Okuno , Shigeki Nagasaka , Masahiro Yoshihara , Akira Umezawa , Satoshi Tsukiyama , Kazushige Kawasaki
IPC: G11C16/30 , H01L25/065 , G11C16/10 , G11C16/14 , G11C16/32 , G11C16/26 , H01L27/10 , G11C16/08 , G11C16/12 , G11C16/34 , G11C16/04
Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
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公开(公告)号：US11714575B2
公开(公告)日：2023-08-01
申请号：US17403542
申请日：2021-08-16
Applicant: KIOXIA CORPORATION
Inventor： Akio Sugahara , Masahiro Yoshihara
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679 , G06F12/10 , G11C16/0483 , G11C16/10 , G11C16/26 , G06F2212/657
Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
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公开(公告)号：US12236139B2
公开(公告)日：2025-02-25
申请号：US18331804
申请日：2023-06-08
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Masahiro Yoshihara
Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
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公开(公告)号：US12198767B2
公开(公告)日：2025-01-14
申请号：US18243258
申请日：2023-09-07
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
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公开(公告)号：US11876080B2
公开(公告)日：2024-01-16
申请号：US17860830
申请日：2022-07-08
Applicant: KIOXIA CORPORATION
Inventor： Masahiro Yoshihara , Toshikazu Watanabe , Nobuharu Miyata , Yasumitsu Nozawa , Tomohito Kawano , Sachie Fukuda , Akiyoshi Itou , Toshimitsu Iwasawa
CPC classification number: H01L25/0657 , H01L24/06 , H01L24/09 , H01L24/48 , H01L24/49 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30 , H01L2224/06165 , H01L2224/09165 , H01L2224/4813 , H01L2224/48105 , H01L2224/4911 , H01L2225/0651 , H01L2225/06506 , H01L2225/06562 , H01L2225/06575 , H01L2924/14511 , H01L2924/182
Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.
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