公开(公告)号：US12027291B2

公开(公告)日：2024-07-02

申请号：US17769855

申请日：2020-09-24

Applicant: KOA CORPORATION

Inventor： Yasushi Akahane ,  Nobuhiko Tamada

IPC: H01C1/14

CPC classification number: H01C1/14

Abstract: A chip component comprises: an insulating substrate on which a resistor serving as a functional element is formed; a pair of internal electrodes (front electrodes, end surface electrodes, and back electrodes) that is formed to cover both end portions of the insulating substrate and connected to the resistor; a barrier layer that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer that is formed on a surface of the barrier layer and mainly composed of tin, and the barrier layer is composed of alloy plating (Ni—P) including nickel and phosphorus, which is formed by electrolytic plating, and a content ratio of phosphorus relative to nickel is set in a range of 0.5% to 5% so that the barrier layer has magnetism.

公开(公告)号：US10192659B2

公开(公告)日：2019-01-29

申请号：US15572847

申请日：2016-04-11

Applicant: KOA Corporation

Inventor： Yasushi Akahane ,  Shinsuke Chihara

IPC: H01C1/148 ,  H01C7/00 ,  H01C1/142

Abstract: Provided is a chip resistor in which cracks, fracture, etc. can be surely prevented from occurring due to thermal stress in solder bonding portions. The chip resistor 1 includes: a ceramic substrate 2 that is shaped like a cuboid; a pair of front electrodes 3 that are provided on lengthwise opposite end portions of a front surface of the ceramic substrate 2; a resistor body 4 that is provided between and connected to the two front electrodes 3; a protective layer 5 that covers the resistor body 4; a pair of back electrodes 6 that are provided on lengthwise opposite end portions of a back surface of the ceramic substrate 2; end-surface electrodes 7 through which the front electrodes 3 and the back electrodes 6 are electrically conductively connected to each other respectively; external electrodes 8 that cover the end-surface electrodes 7; and a pair of insulating resin layers 9 that are provided to cover edge portions of the back electrodes 6; wherein: the pair of insulating resin layers 9 are opposed to each other with interposition of a predetermined interval therebetween on the back surface of the ceramic substrate 2; and at least opposed side end portions of the insulating resin layers 9 are exposed from the external electrodes 8.

公开(公告)号：US12125618B2

公开(公告)日：2024-10-22

申请号：US17769311

申请日：2020-09-24

Applicant: KOA CORPORATION

Inventor： Yasushi Akahane ,  Nobuhiko Tamada

IPC: H01C17/00 ,  C25D3/56 ,  C25D5/12 ,  C25D7/06 ,  C25D21/12 ,  H01C1/032 ,  H01C1/142 ,  H01C17/242

CPC classification number: H01C17/006 ,  C25D3/562 ,  C25D5/12 ,  C25D7/0642 ,  C25D21/12 ,  H01C1/032 ,  H01C1/142 ,  H01C17/242

Abstract: A chip component 10 comprises: an insulating substrate 1 on which a resistor 3 serving as a functional element is formed; a pair of internal electrodes (front electrodes 2, end surface electrodes 6, and back electrodes 5) that is formed to cover both end portions of the insulating substrate 1 and connected to the resistor 3; a barrier layer 8 that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer 9 that is formed on a surface of the barrier layer 8 and mainly composed of tin, and the barrier layer 8 is composed of alloy plating (Ni—P) including nickel and phosphorus, which is formed by electrolytic plating, and a content rate of phosphorus in the alloy plating of an inner region is made different from that of an outer region so that at least the inner region of the barrier layer 8 has magnetic properties.