利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

73 条记录 (耗时 0.018 秒)

    Power saving sensing scheme for solid state memory
    3.
    发明授权
    Power saving sensing scheme for solid state memory 有权
    固态存储器的省电感测方案

    公开(公告)号：US07567465B2

    公开(公告)日：2009-07-28

    申请号：US11847559

    申请日：2007-08-30

    申请人： Chulmin Jung ,  Kang Yong Kim

    发明人： Chulmin Jung ,  Kang Yong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

    摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

    摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

    Bit line charge accumulation sensing for resistive changing memory
    4.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08638597B2

    公开(公告)日：2014-01-28

    申请号：US13476368

    申请日：2012-05-21

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

    BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY
    5.
    发明申请
    BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY 有权
    用于电阻变化存储器的位线电荷累积感测

    公开(公告)号：US20120230094A1

    公开(公告)日：2012-09-13

    申请号：US13476368

    申请日：2012-05-21

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/16

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

    SIGNAL TRANSFER APPARATUS AND METHODS
    6.
    发明申请
    SIGNAL TRANSFER APPARATUS AND METHODS 有权
    信号传输装置和方法

    公开(公告)号：US20100177577A1

    公开(公告)日：2010-07-15

    申请号：US12730994

    申请日：2010-03-24

    申请人： Chulmin Jung ,  Kang Yong Kim

    发明人： Chulmin Jung ,  Kang Yong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括被配置为接收多个信号的多个节点。 信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。 该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。 传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。 传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。 每个传送路径可以仅包括一个存储元件。 公开了包括附加装置，系统和方法的其它实施例。

    Power saving sensing scheme for solid state memory
    7.
    发明授权
    Power saving sensing scheme for solid state memory 有权
    固态存储器的省电感测方案

    公开(公告)号：US07961526B2

    公开(公告)日：2011-06-14

    申请号：US12502932

    申请日：2009-07-14

    申请人： Chulmin Jung ,  Kang Yong Kim

    发明人： Chulmin Jung ,  Kang Yong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

    摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

    摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

    Bit line charge accumulation sensing for resistive changing memory
    8.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08203869B2

    公开(公告)日：2012-06-19

    申请号：US12326184

    申请日：2008-12-02

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域在电磁变化存储单元和栅极之间电连接。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。