公开(公告)号：US09899064B2

公开(公告)日：2018-02-20

申请号：US15583734

申请日：2017-05-01

申请人： Micron Technology, Inc.

发明人： Glen E. Hush

IPC分类号： G11C5/06 ,  G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/1036 ,  G11C5/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1048 ,  G11C7/12 ,  G11C19/28 ,  G11C2207/005

摘要： The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.

公开(公告)号：US09659612B1

公开(公告)日：2017-05-23

申请号：US15166780

申请日：2016-05-27

申请人： SK hynix Inc.

发明人： Yun Gi Hong

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C7/1063 ,  G11C7/103 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/109 ,  G11C7/12 ,  G11C7/22 ,  G11C19/28 ,  G11C2207/107

摘要： A semiconductor memory apparatus may include a data storage region, a pipe register group, and an output driver. The data storage region may store data and output stored data as pipe input data. The pipe register group may include a plurality of pipe registers. In response to a plurality of coupling enable signals, a plurality of pipe input signals and a plurality of pipe output signals, the pipe register group may determine a number of pipe registers receiving the pipe input data and outputting pipe output data. The output driver may drive the pipe output data and transmit output data.

公开(公告)号：US08854873B1

公开(公告)日：2014-10-07

申请号：US13464926

申请日：2012-05-04

申请人： Shane Charles Hollmer ,  John Dinh ,  Derric Jawaher Herman Lewis

发明人： Shane Charles Hollmer ,  John Dinh ,  Derric Jawaher Herman Lewis

IPC分类号： G11C11/4091

CPC分类号： G11C7/1087 ,  G11C7/103 ,  G11C7/106 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0083 ,  G11C2013/0088

摘要： A memory device can include at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions; a read circuit configured to apply the sense conditions to selected elements and detect changes in property of the selected elements to generate read data; a latch circuit configured to store read data from the read circuit; and a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit.

摘要翻译： 存储器件可以包括至少一个阵列，其包括在至少两个不同状态之间可编程的多个元件，每个状态在施加的感测条件下具有与特性变化不同的时间; 读取电路，被配置为将感测条件应用于所选择的元素，并且检测所选元素的属性的变化以产生读取数据; 锁存电路，被配置为存储来自读取电路的读取数据; 以及传送路径，被配置为在读取电路和锁存电路之间提供并行数据传送路径。

公开(公告)号：US20140281101A1

公开(公告)日：2014-09-18

申请号：US14288153

申请日：2014-05-27

申请人： STMicroelectronics International N.V.

发明人： Sandeep ROHILLA

IPC分类号： G06F13/28

CPC分类号： G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

摘要： In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

摘要翻译： 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US08762632B2

公开(公告)日：2014-06-24

申请号：US13336342

申请日：2011-12-23

申请人： Sandeep Rohilla

发明人： Sandeep Rohilla

IPC分类号： G06F12/00

CPC分类号： G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

摘要： In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

摘要翻译： 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US20130117476A1

公开(公告)日：2013-05-09

申请号：US13291703

申请日：2011-11-08

申请人： William V. Miller ,  Robert D. Kenney ,  Charles E. Pope

发明人： William V. Miller ,  Robert D. Kenney ,  Charles E. Pope

IPC分类号： G06F3/00

CPC分类号： G11C7/103 ,  G11C7/106

摘要： Techniques are disclosed relating to buffer circuits. In one embodiment, a buffer circuit is disclosed that includes memory unit and an output register. The memory unit is configured to store a plurality of buffer entries and a first pointer to a current one of the plurality of buffer entries. The output register is coupled to an output of the memory unit. The buffer circuit is configured to perform a read operation by outputting a current value of the output register and storing a value of the current buffer entry in the output register. The buffer circuit is configured to update the first pointer in response to the read operation.

摘要翻译： 公开了涉及缓冲电路的技术。 在一个实施例中，公开了包括存储器单元和输出寄存器的缓冲器电路。 存储器单元被配置为将多个缓冲器条目和第一指针存储到多个缓冲器条目中的当前缓冲器条目。 输出寄存器耦合到存储器单元的输出端。 缓冲电路被配置为通过输出输出寄存器的当前值并将当前缓冲器条目的值存储在输出寄存器中来执行读取操作。 缓冲电路被配置为响应于读取操作来更新第一指针。

公开(公告)号：US08218388B2

公开(公告)日：2012-07-10

申请号：US12614909

申请日：2009-11-09

申请人： Tetsuya Kaneko

发明人： Tetsuya Kaneko

IPC分类号： G11C7/00

CPC分类号： G11C7/103 ,  G11C7/1039

摘要： Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of byte selectors which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale.

摘要翻译： 提供了一种可能具有减小的电路规模的半导体存储器件的读取电路和半导体存储器件。 在半导体存储器件的读取电路的多个读出放大器中，用于从串行输出端子串行读取数据，如果在确定地址之前的预定时间可以选择确定地址的字节选择器的数量是 四个总共仅需要四个读出放大器，因此读取电路和半导体存储器件的电路规模缩小。

公开(公告)号：US08190851B2

公开(公告)日：2012-05-29

申请号：US12617758

申请日：2009-11-13

申请人： Kwang-jin Lee ,  Young-kug Moon ,  Kwang-ho Kim

发明人： Kwang-jin Lee ,  Young-kug Moon ,  Kwang-ho Kim

IPC分类号： G06F12/00

CPC分类号： G06F12/0215 ,  G06F12/0238 ,  G06F2212/7203 ,  G11C7/103 ,  G11C13/0004 ,  G11C13/004 ,  Y02D10/13

摘要： A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.

摘要翻译： 电阻可变存储器件包括电阻可变存储单元阵列，预取电阻可变存储单元阵列的读取数据的数据寄存器，从数据寄存器接收预取的读取数据并输出接收的数据的数据输出单元，以及 页面模式设置单元，其将第一页面模式和第二页面模式之一设置为页面模式。 在第一页面模式中，数据输出单元顺序地读取在数据寄存器中预取的读取数据，因为顺序地接收页面地址，而在第二页面模式中，数据输出单元顺序地读取在数据寄存器中预读取的读取数据 已经接收到多个页地址中的起始页地址。

公开(公告)号：US07974124B2

公开(公告)日：2011-07-05

申请号：US12490655

申请日：2009-06-24

申请人： Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

发明人： Hardwell Chibvongodze ,  Manabu Sakai ,  Teruhiko Kamei

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

摘要： Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

摘要翻译： 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 在第一组实施例中，具有阵列列的移位寄存器链具有以循环布置的列。 例如，当指针沿着阵列的第一方向移动时，可以评估每隔一列或列组，随着指针在另一个方向上向后移动，另外一半的列被访问。 另一组实施例将列分成两组，并且使用一对交错指针，每半组一列，以半速计时。 为了控制两个组的访问，每个集合都连接到相应的中间数据总线。 然后将中间数据总线连接到以全速计时的组合数据总线。

公开(公告)号：US07961526B2

公开(公告)日：2011-06-14

申请号：US12502932

申请日：2009-07-14

申请人： Chulmin Jung ,  Kang Yong Kim

发明人： Chulmin Jung ,  Kang Yong Kim

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。