摘要:
A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要:
An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译:错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器,基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器,以及 选择器电路,其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路被切换以从CPU输出数据时,基于从选择器电路输出的错误检测数据,误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断 。
摘要:
An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译:错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器,基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器,以及 选择器电路,其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路被切换以从CPU输出数据时,基于从选择器电路输出的错误检测数据,误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断 。
摘要:
A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要:
A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要:
A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要:
A data search device that is provided in a communication apparatus detects a memory area storing data to be transmitted from a memory unit having memory areas defined by IDs allotted to data. The data search device includes: a first flag that is provided for each of the memory areas of the memory unit, and indicate whether the data in the corresponding memory area is updated; a second flag that is provided for each group consisting of a predetermined number of the first flags, and indicates a data update state when at least one set of data in the first flags in the corresponding group indicates an updated state; and a search control unit that detects the memory area storing the data to be transmitted, by searching for the corresponding first flag after detecting the second flag.
摘要:
A data search device that is provided in a communication apparatus detects a memory area storing data to be transmitted from a memory unit having memory areas defined by IDs allotted to data. The data search device includes: a first flag that is provided for each of the memory areas of the memory unit, and indicate whether the data in the corresponding memory area is updated; a second flag that is provided for each group consisting of a predetermined number of the first flags, and indicates a data update state when at least one set of data in the first flags in the corresponding group indicates an updated state; and a search control unit that detects the memory area storing the data to be transmitted, by searching for the corresponding first flag after detecting the second flag.
摘要:
A switching regulator is composed of digital circuits only. A switching regulator (30) comprises a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver (2). An output terminal (Q) of an RS flip-flop (5) is connected to one input end of the OR gate (6), the output of a timer (40c) is applied to a set terminal (S) of the RS flip-flop (5), and the output of a comparator (4) is applied to a reset terminal (R1) through an OR gate (7). At a non-reverse input end of the comparator (4), a reference voltage (VE) is applied by a D/A convertor (40b), while a feedback voltage (VFB) is applied to a reverse input end. Accordingly, chopping of the switching transistor (1) is done on the basis of a rectangular pulse.
摘要:
(1) a compound represented by the following formula (I): ##STR1## wherein R represents a hydrocarbon group or heterocyclic group which may be substituted; the ring A represents a pyridine ring having a substituent or a thiazole ring which may be substituted; or a pharmaceutically acceptable salt thereof, and a method of its production, and(2) an endothelin receptor antagonist, an cathepsin B inhibitor or a bone resorption suppressor having as an active ingredient a compound represented by the following formula (I'): ##STR2## wherein R has the same definition as in term (1); the ring A' represents a pyridine ring or thiazole ring which may be substituted; or a pharmaceutically acceptable salt thereof.