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    Memory element and memory device comprising memory layer positioned between first and second electrodes
    1.
    发明授权
    Memory element and memory device comprising memory layer positioned between first and second electrodes 有权
    存储元件和存储器件包括位于第一和第二电极之间的存储器层

    公开(公告)号：US07786459B2

    公开(公告)日：2010-08-31

    申请号：US11280561

    申请日：2005-11-15

    申请人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama ,  Tetsuya Mizuguchi

    发明人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama ,  Tetsuya Mizuguchi

    IPC分类号： H01L29/02

    CPC分类号： G11C13/0011 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

    摘要： A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a resistance of the memory element 10 is changed by a voltage applied to the memory element 10 to perform recording of information, and in an erasing process of changing from a recorded state of low resistance value of the memory element 10 to an erased state of high resistance value of the memory element 10, a fluctuation, which is caused by an increase of the voltage applied to the memory element 10, of the resistance value of the memory element 10 at the end of the erasing process is within ten times at a maximum.

    摘要翻译： 存储元件10包括位于第一电极2和第二电极6之间的存储层4，其中选自Cu，Ag和Zn的元素包含在存储层4中或与存储器接触的层3中 层4，存储元件10的电阻被施加到存储元件10的电压改变以进行信息的记录，并且在从存储元件10的低电阻值的记录状态改变为擦除的擦除处理 存储元件10的高电阻值的状态，由擦除处理结束时的存储元件10的电阻值的升高引起的由存储元件10施加的电压引起的波动为十倍以内 最大。

    Memory element and memory device
    2.
    发明申请
    Memory element and memory device 有权
    存储器元件和存储器件

    公开(公告)号：US20060104106A1

    公开(公告)日：2006-05-18

    申请号：US11280561

    申请日：2005-11-15

    申请人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama ,  Tetsuya Mizuguchi

    发明人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama ,  Tetsuya Mizuguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

    摘要： A memory element is provided in which recording and erasure of information can be performed easily and stably. A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a resistance of the memory element 10 is changed by a voltage applied to the memory element 10 to perform recording of information, and in an erasing process of changing from a recorded state of low resistance value of the memory element 10 to an erased state of high resistance value of the memory element 10, a fluctuation, which is caused by an increase of the voltage applied to the memory element 10, of the resistance value of the memory element 10 at the end of the erasing process is within ten times at a maximum.

    摘要翻译： 提供了一种存储元件，其中可以容易且稳定地执行信息的记录和擦除。 存储元件10包括位于第一电极2和第二电极6之间的存储层4，其中选自Cu，Ag和Zn的元素包含在存储层4中或与存储器接触的层3中 层4，存储元件10的电阻被施加到存储元件10的电压改变以进行信息的记录，并且在从存储元件10的低电阻值的记录状态改变为擦除的擦除处理 存储元件10的高电阻值的状态，由擦除处理结束时的存储元件10的电阻值的升高引起的由存储元件10施加的电压引起的波动为十倍以内 最大。

    Storage device
    4.
    发明申请
    Storage device 有权
    储存设备

    公开(公告)号：US20050121697A1

    公开(公告)日：2005-06-09

    申请号：US10999050

    申请日：2004-11-29

    申请人： Minoru Ishida ,  Katsuhisa Aratani ,  Akira Kouchiyama ,  Tomohito Tsushima

    发明人： Minoru Ishida ,  Katsuhisa Aratani ,  Akira Kouchiyama ,  Tomohito Tsushima

    IPC分类号： G11C16/04 ,  G11C13/02 ,  H01L27/10 ,  H01L31/109 ,  H01L45/00

    CPC分类号： G11C13/0011 ,  G11C13/0009 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/144 ,  H01L45/146

    摘要： A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.

    摘要翻译： 存储装置包括第一电极，面对第一电极的第二电极，设置在第一电极和第二电极之间的电极间材料层，以及向第一和第二电极施加预定电压的电压施加单元。 此外，通过向第一和第二电极施加电压而可变化为电极反应抑制层的氧化还原活性物质被包含在被电场覆盖的区域中，电场在施加电压时产生，并且 电极反应抑制层沿着第二电极和电极间材料层之间的界面区域形成，或者改变其面积，或者根据第一和第二电压的施加条件而消失。

    Memory device having variable resistive memory element
    6.
    发明授权
    Memory device having variable resistive memory element 有权
    具有可变电阻存储元件的存储器件

    公开(公告)号：US07145791B2

    公开(公告)日：2006-12-05

    申请号：US11042959

    申请日：2005-01-25

    申请人： Tomohito Tsushima ,  Katsuhisa Aratani ,  Akira Kouchiyama

    发明人： Tomohito Tsushima ,  Katsuhisa Aratani ,  Akira Kouchiyama

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0009 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    摘要： A memory device is obtained in which stable recording of information can be performed and a period of time required for the recording of information can be shortened. The memory device includes a memory cell C formed of a memory element Amn having a characteristic in which a resistance value changes when applying between both ends of the memory element Amn a voltage equal to or more than a threshold voltage and a circuit element Tmn as a load connected in series to the memory element Amn; and when an operation to change the memory element Amn from a state of high resistance value to a state of low resistance value is defined as writing and when a voltage applied between both ends of the memory element Amn and the circuit element Tmn is equal to or more than a certain voltage value which is larger than the threshold voltage, the memory device has a characteristic in which a combined resistance value of the memory element Amn and the circuit element Tmn in the memory cell C after writing becomes almost constant value irrespective of the magnitude of applied voltage.

    摘要翻译： 获得可以执行信息的稳定记录并且可以缩短记录信息所需的时间段的存储器件。 存储器件包括由存储元件Amn形成的存储单元C，该存储单元Amn具有当存储元件Amn的两端施加等于或大于阈值电压的电压和电路元件Tmn之间电阻值变化的特性时 负载串联连接到存储元件Amn; 并且当将存储元件Amn从高电阻值状态改变为低电阻值的状态的操作被定义为写入时，并且当存储元件Amn和电路元件Tmn的两端之间施加的电压等于或等于 大于阈值电压的一定电压值，存储器件具有这样的特性，其中存储元件Amn和写入后存储单元C中的电路元件Tmn的组合电阻值几乎是恒定值，而与 施加电压的大小。

    Memory element and memory device comprising memory layer positioned between first and second electrodes
    10.
    发明申请
    Memory element and memory device comprising memory layer positioned between first and second electrodes 有权
    存储元件和存储器件包括位于第一和第二电极之间的存储器层

    公开(公告)号：US20080089112A1

    公开(公告)日：2008-04-17

    申请号：US11998917

    申请日：2007-12-03

    申请人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama

    发明人： Katsuhisa Aratani ,  Tomohito Tsushima ,  Akira Kouchiyama

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

    摘要： A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a resistance of the memory element 10 is changed by a voltage applied to the memory element 10 to perform recording of information, and in an erasing process of changing from a recorded state of low resistance value of the memory element 10 to an erased state of high resistance value of the memory element 10, a fluctuation, which is caused by an increase of the voltage applied to the memory element 10, of the resistance value of the memory element 10 at the end of the erasing process is within ten times at a maximum.

    摘要翻译： 存储元件10包括位于第一电极2和第二电极6之间的存储层4，其中选自Cu，Ag和Zn的元素包含在存储层4中或与存储器接触的层3中 层4，存储元件10的电阻被施加到存储元件10的电压改变以进行信息的记录，并且在从存储元件10的低电阻值的记录状态改变为擦除的擦除处理 存储元件10的高电阻值的状态，由擦除处理结束时的存储元件10的电阻值的升高引起的由存储元件10施加的电压引起的波动为十倍以内 最大。