公开(公告)号：US5367490A

公开(公告)日：1994-11-22

申请号：US967133

申请日：1992-10-27

申请人： Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

发明人： Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C7/22 ,  H03K5/24 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C5/025 ,  G11C7/10 ,  H03K5/2418

摘要： Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

摘要翻译： 公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是 以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

公开(公告)号：US5014242A

公开(公告)日：1991-05-07

申请号：US281399

申请日：1988-12-08

申请人： Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

发明人： Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C7/22 ,  H03K5/24

CPC分类号： G11C7/22 ,  G11C5/025 ,  G11C7/10 ,  H03K5/2418

摘要： Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

摘要翻译： 公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是 以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

公开(公告)号：US08782597B2

公开(公告)日：2014-07-15

申请号：US13428399

申请日：2012-03-23

申请人： Lan Wang ,  Hiroshi Murayama ,  Akira Hosokawa

发明人： Lan Wang ,  Hiroshi Murayama ,  Akira Hosokawa

IPC分类号： G06F17/30 ,  G06F15/00

CPC分类号： G06F8/65

摘要： According to one embodiment, an ontology updating apparatus includes a generation unit, an updating unit, a detection unit and a notification unit. The generation unit generates updating reference relationship. The updating unit updates a first class and a first package. The detection unit detects, using the updating reference relationship, whether at least one of target packages are comprised in the updating reference packages of the updated first package, the target packages each indicating a package to be updated and associated with the updated first class. The notification unit generates, if there is the target package, an update notice that the target package needs to be updated.

摘要翻译： 根据一个实施例，本体更新装置包括生成单元，更新单元，检测单元和通知单元。 生成单元生成更新参考关系。 更新单元更新第一类和第一包。 所述检测单元使用所述更新参考关系来检测所述更新的第一包的更新参考包中是否包括至少一个目标包，所述目标包指示要更新的包并且与所述更新的第一类相关联。 如果存在目标包，则通知单元生成需要更新目标包的更新通知。

公开(公告)号：US20120141455A1

公开(公告)日：2012-06-07

申请号：US12809191

申请日：2008-12-19

申请人： Hideo Ohmae ,  Hiroshi Murayama ,  Naohiro Takimoto ,  Yuji Sakamoto ,  Osamu Kanauchi ,  Mikio Katayama ,  Hiroyuki Watanabe ,  Yuta Komano

发明人： Hideo Ohmae ,  Hiroshi Murayama ,  Naohiro Takimoto ,  Yuji Sakamoto ,  Osamu Kanauchi ,  Mikio Katayama ,  Hiroyuki Watanabe ,  Yuta Komano

IPC分类号： A23L1/308 ,  A23L1/105 ,  A61P29/00 ,  A61K36/899 ,  A61P1/00

CPC分类号： A61K36/899 ,  A23L7/107 ,  A23L7/115 ,  A23L33/22 ,  C12P19/04 ,  C12P19/14

摘要： This invention provides a product safe for treating, improving or preventing an inflammatory bowel disease such as ulcerative colitis, and provides a product comprising an insoluble dietary fiber obtained by enzymatic treatment of seeds of a grain plant(s) or germinated young seeds thereof, as well as a food or drink or medicament comprising the product.

摘要翻译： 本发明提供一种治疗，改善或预防溃疡性结肠炎等炎症性肠病的产品安全性，并且提供包含通过酶处理种子植物或其发芽的幼苗的种子获得的不溶性膳食纤维的产品，作为 以及包含该产品的食品或饮料或药物。

公开(公告)号：US07532283B2

公开(公告)日：2009-05-12

申请号：US10530828

申请日：2004-08-10

申请人： Tomoya Yano ,  Norimasa Furukawa ,  Hiroshi Murayama

发明人： Tomoya Yano ,  Norimasa Furukawa ,  Hiroshi Murayama

IPC分类号： G02F1/1335

CPC分类号： G02F1/133634 ,  G02B5/3083 ,  G02F1/134363 ,  G02F2001/133749

摘要： In case polarization plates (10A, 10B) including protective layers whose phase difference is negative are used, a retardation film optimized for the negative phase difference is placed in a position (P1) between a liquid crystal plane (20) and outgoing-side polarization plate (10A), in a position (P2) between the outgoing-side polarization plate (10A) and liquid crystal plate (20) or in both the positions (P1, P2) to reduce the leakage of black-level light directed at an angle 45 deg. Thus, in the in-plane switching (IPS) mode type liquid crystal display device, optical compensation is made to improve the viewing angle in black display.

摘要翻译： 在使用包括相位差为负的保护层的偏振板（10A，10B）的情况下，将针对负相位差优化的延迟膜设置在液晶面（20）和出射侧极化之间的位置（P1） （10A），在出射侧偏振板（10A）和液晶板（20）之间的位置（P2）或两个位置（P1，P2）处，以减少指向 角度45度 因此，在平面切换（IPS）模式型液晶显示装置中，进行光学补偿以改善黑色显示中的视角。

公开(公告)号：US20090100001A1

公开(公告)日：2009-04-16

申请号：US10580271

申请日：2006-03-02

申请人： Noriko Minamino ,  Hiroshi Murayama

发明人： Noriko Minamino ,  Hiroshi Murayama

IPC分类号： G06F7/00

CPC分类号： G06F17/30589 ,  G06F17/30607

摘要： Information on a referenced class or a referenced property is extracted from at least one referenced dictionary having a referencing relation with a referencing dictionary having the hierarchical structure, in which lower classes inherit the properties of upper classes; the extracted information is added to the referencing dictionary and organized; the extracted detailed information is outputted organized referencing dictionary. Thus, the detailed information on an imported property may be acquired simply at the side of the referencing dictionary. In addition, since only the information on the referenced class or property in the referenced dictionary is separately extracted, traffic of the dictionary data may be reduced, and the efficient inter-dictionary data exchange can be realized.

摘要翻译： 从具有具有分级结构的引用字典的引用关系的至少一个引用的字典中提取关于被引用类或引用属性的信息，其中较低级继承上级的属性; 提取的信息被添加到引用字典并组织; 提取的详细信息被输出有组织的参考字典。 因此，可以简单地在引用字典的一侧获取关于导入的属性的详细信息。 另外，由于只有在引用的字典中引用的类别或属性的信息被单独提取，所以字典数据的流量可以被减少，并且可以实现有效的字典间数据交换。

公开(公告)号：US5291287A

公开(公告)日：1994-03-01

申请号：US888500

申请日：1992-05-27

申请人： Hiroshi Murayama ,  Akira Shirahama ,  Takahiko Tamura ,  Yumiko Mito ,  Shinichirou Miyazaki

发明人： Hiroshi Murayama ,  Akira Shirahama ,  Takahiko Tamura ,  Yumiko Mito ,  Shinichirou Miyazaki

IPC分类号： H04N5/06 ,  H04N5/10 ,  H04N5/12 ,  H04N5/04

CPC分类号： H04N5/12

摘要： A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.

摘要翻译： 垂直同步处理电路包括用于对与水平同步同步的时钟信号进行计数的计数器。 信号，用于响应于由于非标准信号禁止复位的预定限制内的垂直同步信号而复位计数器的电路，用于存储在复位定时计数的数据的存储器和用于改变预定极限的电路 根据来自存储器的数据，由于非标准信号而禁止复位。 如果在计数器计数预定数量的时钟信号的情况下识别电路检测到垂直同步间隔的存在，则还可以提供用于鉴别垂直同步间隔的存在的电路以及用于复位计数器的第二复位电路 不是预定极限内的垂直同步脉冲。

公开(公告)号：US4794106A

公开(公告)日：1988-12-27

申请号：US902002

申请日：1986-08-28

申请人： Yasuji Takashima ,  Shigeo Tanaka ,  Kenji Tsunoda ,  Ichirou Kawamata ,  Hiroshi Murayama

发明人： Yasuji Takashima ,  Shigeo Tanaka ,  Kenji Tsunoda ,  Ichirou Kawamata ,  Hiroshi Murayama

IPC分类号： A61K9/00 ,  A61K9/06 ,  A61K31/57 ,  A61K47/00 ,  A61P29/00 ,  A61K31/56 ,  A61K31/58 ,  C07J5/00

CPC分类号： A61K9/0014 ,  A61K31/57 ,  A61K9/06 ,  Y10S514/943 ,  Y10S514/969

摘要： An oil-in-water type cream comprising(a) 0.01 to 0.5% by weight of hydrocortisone butyrate proponate,(b) 5 to 50% by weight of a higher paraffinic hydrocarbon,(c) 3 to 15% by weight of a surface-active agent,(d) 30 to 65% by weight of purified water,(e) not more than 20% by weight of a monohydric higher alcohol,(f) not more than 20% by weight of a dihdyric or trihydric alcohol, and(g) a pharmaceutically acceptable acid in an amount required to adjust the pH of the cream to a value in the range of 3.5 to 6.5 when it is diluted with water to 20 times its volume.

摘要翻译： 一种水包油型乳膏，其包含（a）0.01至0.5重量％的丙酸氢化可的松酸氢可的松，（b）5至50重量％的较高链烷烃，（c）3至15重量％的表面 活性剂，（d）30〜65重量％的纯水，（e）20重量％以下的一元高级醇，（f）20重量％以下的二羟基或三元醇， 和（g）当将其用水稀释至其体积的20倍时，将膏体的pH调节至3.5至6.5范围内所需的量的药学上可接受的酸。

公开(公告)号：US4757444A

公开(公告)日：1988-07-12

申请号：US685134

申请日：1984-12-21

申请人： Tomoo Aoyama ,  Yuuji Aoki ,  Hiroshi Murayama

发明人： Tomoo Aoyama ,  Yuuji Aoki ,  Hiroshi Murayama

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347

CPC分类号： G06F15/8076

摘要： There is provided a vector processor based on a pipeline control method in which a cyclic operation is divided into a plurality of stages and processed. This processor comprises a vector register controller for dividing an operating process into a plurality of fundamental process units and controlling these units, and a phase generator for allowing the vector register controller to time-sharingly make the vector processor operative. This vector processor reads out data from vector registers in which vector elements are stored, operates this data and writes the result of operation into the vector register. With this vector processor, a cyclic operation can be processed in parallel at a high speed without causing a remarkable increase in hardware.

摘要翻译： 提供了一种基于流水线控制方法的向量处理器，其中循环操作被划分为多个级并被处理。 该处理器包括用于将操作过程分成多个基本处理单元并控制这些单元的向量寄存器控制器，以及用于允许向量寄存器控制器分时地使向量处理器可操作的相位发生器。 该向量处理器从存储向量元素的向量寄存器中读出数据，操作该数据并将操作结果写入向量寄存器。 使用该向量处理器，可以高速并行地处理循环操作，而不会导致硬件显着增加。

公开(公告)号：US4658355A

公开(公告)日：1987-04-14

申请号：US449659

申请日：1982-12-14

申请人： Yasuhiko Hatakeyama ,  Hiroshi Murayama

发明人： Yasuhiko Hatakeyama ,  Hiroshi Murayama

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347

CPC分类号： G06F15/8053 ,  G06F9/3867

摘要： In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.

摘要翻译： 在流水线运算装置中，算术运算被划分为多个级，并且在每个级中以重叠的方式进行处理。 每个阶段都提供算术电路。 寄存器分别将表示算术运算内容的控制信息保存到各运算电路或预定数量的运算电路。 由每个寄存器保持的控制信息被直接提供给相关联的运算电路或解码之后，以指令由每个运算电路执行的算术运算。 每个寄存器保持的控制信息以及每个运算电路的输出分别被传送到后级的寄存器和运算电路。