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公开(公告)号：US5949719A
公开(公告)日：1999-09-07
申请号：US190905
申请日：1998-11-12
申请人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C13/00
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
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2.发明授权Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array 失效存储器子阵列与存储器阵列中的分层位线结构之间的选择性连接
公开(公告)号：US6023421A
公开(公告)日：2000-02-08
申请号：US190920
申请日：1998-11-12
申请人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C5/06
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译： 提供了具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。
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公开(公告)号：US6038192A
公开(公告)日：2000-03-14
申请号：US189391
申请日：1998-11-10
申请人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译： 提供具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。
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公开(公告)号：US6075745A
公开(公告)日：2000-06-13
申请号：US190628
申请日：1998-11-12
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译： 提供具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。
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公开(公告)号：US5914906A
公开(公告)日：1999-06-22
申请号：US575312
申请日：1995-12-20
申请人： Joseph Andrew Iadanza , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Joseph Andrew Iadanza , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
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