公开(公告)号：US20220093685A1

公开(公告)日：2022-03-24

申请号：US17346478

申请日：2021-06-14

Applicant: Kioxia Corporation

Inventor： Yoshiki KAMATA ,  Misako MOROTA ,  Yukihiro NOMURA ,  Yoshiaki ASAO

IPC: H01L27/24 ,  H01L27/11507 ,  H01L27/11514

Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

公开(公告)号：US20230102229A1

公开(公告)日：2023-03-30

申请号：US17693935

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yoshiki KAMATA ,  Yoshiaki ASAO ,  Yukihiro NOMURA ,  Misako MOROTA ,  Daisaburo TAKASHIMA ,  Takahiko IIZUKA ,  Shigeru KAWANAKA

IPC: G11C13/00 ,  G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

公开(公告)号：US20240049479A1

公开(公告)日：2024-02-08

申请号：US18177064

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Yuki ITO ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA ,  Yoshiki KAMATA

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/845 ,  H10B63/34 ,  H10B61/22

Abstract: A variable resistance non-volatile memory includes a memory cell including a core portion extending in a first direction above a semiconductor substrate, a variable resistance layer extending in a first direction and in contact with the core portion, a semiconductor layer extending in a first direction and in contact with the variable resistance layer, an insulator layer extending in a first direction and in contact with the semiconductor layer, and a first voltage application electrode extending in a second direction crossing the first direction and in contact with the insulator layer. An impurity concentration of the semiconductor layer is non-uniform, such that an impurity concentration of a first portion of the semiconductor layer in contact with the insulator layer is at least ten times higher than an impurity concentration of a second portion of the semiconductor layer in contact with the variable resistance layer.

公开(公告)号：US20230413584A1

公开(公告)日：2023-12-21

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/75 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C13/0069

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20210399049A1

公开(公告)日：2021-12-23

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20210376236A1

公开(公告)日：2021-12-02

申请号：US17201356

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Bairu YAN ,  Yoshiki KAMATA ,  Kazuhiko YAMAMOTO

IPC: H01L45/00 ,  H01L27/24

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a resistive layer provided between the first electrode and the second electrode, containing at least one of antimony (Sb) and bismuth (Bi) as a first element, and tellurium (Te) as a second element, and having a variable resistance value. The resistive layer includes a first layer having a hexagonal crystal structure containing the first element and the second element. The first layer contains a group 14 element as a third element.