公开(公告)号：US20240096413A1

公开(公告)日：2024-03-21

申请号：US18177704

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Natsuki SAKAGUCHI ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

CPC classification number: G11C16/0433 ,  G11C7/065 ,  G11C16/24

Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

公开(公告)号：US20220301643A1

公开(公告)日：2022-09-22

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Reiko SUMI ,  Reika TANAKA ,  Masumi SAITOH

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US20220301636A1

公开(公告)日：2022-09-22

申请号：US17447464

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Kyosuke SANO ,  Kazutaka IKEGAMI ,  Takashi MAEDA ,  Rieko FUNATSUKI

IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/30

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

公开(公告)号：US20240062822A1

公开(公告)日：2024-02-22

申请号：US18500520

申请日：2023-11-02

Applicant: Kioxia Corporation

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  H10B41/10

Abstract: A semiconductor memory device includes a first to eighth memory cell groups arranged along a first direction, a first word line extending in the first direction and a first to an eighth sense amplifier groups configured to be capable of supplying voltages to the first to the eighth memory cell groups, respectively. Each of the first to the eighth memory cell groups includes a plurality of memory cells and a plurality of bit lines each connected to the plurality of memory cells. In a write operation of supplying a program voltage to the first word line, the first sense amplifier group supplies a first voltage to the bit line connected to a write target memory cell of the first memory cell group, and the second sense amplifier group supplies a second voltage to the bit line connected to a write target memory cell of the second memory cell group.

公开(公告)号：US20230197148A1

公开(公告)日：2023-06-22

申请号：US17806346

申请日：2022-06-10

Applicant: Kioxia Corporation

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/3459

Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

公开(公告)号：US20210090665A1

公开(公告)日：2021-03-25

申请号：US16906140

申请日：2020-06-19

Applicant: Kioxia Corporation

Inventor： Rieko FUNATSUKI ,  Takahiko HARA ,  Takashi MAEDA

IPC: G11C16/26 ,  G11C16/04

Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

公开(公告)号：US20240071477A1

公开(公告)日：2024-02-29

申请号：US18500478

申请日：2023-11-02

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Rieko FUNATSUKI ,  Nobuyuki MOMO ,  Hidehiro SHIGA

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.

公开(公告)号：US20230413584A1

公开(公告)日：2023-12-21

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko IIZUKA ,  Daisaburo TAKASHIMA ,  Ryu OGIWARA ,  Rieko FUNATSUKI ,  Yoshiki KAMATA ,  Misako MOROTA ,  Yoshiaki ASAO ,  Yukihiro NOMURA

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/75 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C13/0069

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20220093152A1

公开(公告)日：2022-03-24

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US20230297245A1

公开(公告)日：2023-09-21

申请号：US17899974

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Sumiko DOMAE ,  Kazutaka IKEGAMI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/0653

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.