公开(公告)号：US20100052753A1

公开(公告)日：2010-03-04

申请号：US12514115

申请日：2007-10-26

申请人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

发明人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/00

CPC分类号： G06F1/10 ,  H03K23/507 ,  H03L7/0814 ,  H03L7/16

摘要： A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

摘要翻译： 分频比由N / M（M和N是正整数，满足M> N）调节的时钟信号分频电路包括：可变延迟电路，其基于对输入时钟的控制值给出预定的延迟量 信号CKI输出输出时钟信号CKO; 以及可变延迟控制电路，当相加结果为N以上时，累积地将通过从输入时钟信号CKI的每个周期从M中减去N而获得的值执行从相加结果中减去N的计算，以获得计算结果K ，并且将对应于输入时钟信号CKI的一个周期的可变延迟电路中的最大延迟量计算为与最大延迟量的K / N的延迟量相对应的控制值，以将控制值赋予该变量 延时电路。

公开(公告)号：US20080018372A1

公开(公告)日：2008-01-24

申请号：US11575168

申请日：2005-09-16

申请人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

发明人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

IPC分类号： H03H11/16

CPC分类号： H03K5/00006 ,  G06F1/06 ,  H03K5/13 ,  H03K5/1565 ,  H03K2005/00052 ,  H03L7/07 ,  H03L7/0814

摘要： A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.

摘要翻译： 时钟转换电路（1）接收并且将具有1 /（fxm）相位差的频率f的m相时钟转换成具有1 /（fxn）相位差的频率f的n相时钟。 单相时钟发生电路（2）接收具有1 /（fxn）的相位差等效时间的频率f的n相时钟，以产生与n频率的上升沿或下降沿同步的单相时钟。 相位时钟。 由于输入到时钟转换电路（1）的m相时钟的频率为'f'，所以如果确定了单相时钟的期望频率，则可以从下列公式得到'n'：频率 单相时钟等于（fxn）。 该值“n”被设置为时钟转换电路（1），从而从频率f的m相时钟获得频率f的n相时钟，以提供期望频率的单相时钟。

公开(公告)号：US08242814B2

公开(公告)日：2012-08-14

申请号：US11575168

申请日：2005-09-16

申请人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

发明人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

IPC分类号： H03B19/00

CPC分类号： H03K5/00006 ,  G06F1/06 ,  H03K5/13 ,  H03K5/1565 ,  H03K2005/00052 ,  H03L7/07 ,  H03L7/0814

摘要： A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.

摘要翻译： 时钟转换电路（1）接收并将具有1 /（f×m）相位差的频率f的m相时钟转换为相位差为1 /（f×m）的频率f的n相时钟 n）。 单相时钟发生电路（2）接收具有1 /（f×n）的相位差当量时间的频率f的n相时钟，以产生与相位差等效时间的上升沿或下降沿同步的单相时钟 n相时钟。 由于输入到时钟转换电路（1）的m相时钟的频率为'f'，所以如果确定了单相时钟的期望频率，那么可以从以下等式获得“n”：频率 单相时钟等于（f×n）。 该值“n”被设置为时钟转换电路（1），从而从频率f的m相时钟获得频率f的n相时钟，以提供期望频率的单相时钟。

公开(公告)号：US08635040B2

公开(公告)日：2014-01-21

申请号：US12519837

申请日：2007-12-19

申请人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

发明人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

IPC分类号： G01R13/02

CPC分类号： G01R31/31937 ,  G01R31/31708 ,  G01R31/31726

摘要： A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

摘要翻译： 一种信号测量装置，包括测量与测量的驱动时钟信号同步的测量对象的一组或多组测量单元，并将测量结果作为第一数据输出，以及定时识别单元， 根据测量开始命令，将与每个周期不同的值作为与具有规定周期和速度低于驱动时钟信号的参考信号同步的第二数据输出; 以及与所述驱动时钟信号同步地收集并依次存储所述第一数据和所述第二数据作为一组的存储单元。

公开(公告)号：US07893742B2

公开(公告)日：2011-02-22

申请号：US12514115

申请日：2007-10-26

申请人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

发明人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/00

CPC分类号： G06F1/10 ,  H03K23/507 ,  H03L7/0814 ,  H03L7/16

摘要： A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

摘要翻译： 分频比由N / M（M和N是正整数，满足M> N）调节的时钟信号分频电路包括：可变延迟电路，其基于对输入时钟的控制值给出预定的延迟量 信号CKI输出输出时钟信号CKO; 以及可变延迟控制电路，当相加结果为N以上时，累积地将通过从输入时钟信号CKI的每个周期从M中减去N而获得的值执行从相加结果中减去N的计算，以获得计算结果K ，并且将对应于输入时钟信号CKI的一个周期的可变延迟电路中的最大延迟量计算为与最大延迟量的K / N的延迟量相对应的控制值，以将控制值赋予该变量 延时电路。

公开(公告)号：US07702945B2

公开(公告)日：2010-04-20

申请号：US11575473

申请日：2005-09-16

申请人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

发明人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： G06F1/04

CPC分类号： H04L7/0012 ,  G06F1/12 ,  H04L7/0041

摘要： The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores.

摘要翻译： 本发明涉及能够建立核之间的通信的技术，其能够提供可在每个核心中设置的时钟频率的大的自由度，从而提供确定性的操作，小的通信延迟和高的可靠性。 本发明的目的是通过基于半导体器件内的通信历史分析影响半导体器件的性能的因素，并将分析反映到下一代半导体器件，来提供具有高可靠性的半导体器件。 改进的半导体器件包括用于与时钟信号clkA同步发送数据的核心A，用于接收与时钟信号clkB同步的数据的核心B与时钟信号clkA的上升或下降保持一致，并且 控制器用于控制核心A和核心B之间的通信。控制器以这样的方式进行控制，使得核心B可以仅接收在建立时钟信号clkB之前到达的数据。 控制器将历史记录存储在内核之间的通信状态。

公开(公告)号：US20100042373A1

公开(公告)日：2010-02-18

申请号：US12519837

申请日：2007-12-19

申请人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

发明人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

IPC分类号： G06F15/00

CPC分类号： G01R31/31937 ,  G01R31/31708 ,  G01R31/31726

摘要： A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

摘要翻译： 一种信号测量装置，包括测量与测量的驱动时钟信号同步的测量对象的一组或多组测量单元，并将测量结果作为第一数据输出，以及定时识别单元， 根据测量开始命令，将与每个周期不同的值作为与具有规定周期和速度低于驱动时钟信号的参考信号同步的第二数据输出; 以及与所述驱动时钟信号同步地收集并依次存储所述第一数据和所述第二数据作为一组的存储单元。

公开(公告)号：US20080218225A1

公开(公告)日：2008-09-11

申请号：US11575473

申请日：2005-09-16

申请人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

发明人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/00

CPC分类号： H04L7/0012 ,  G06F1/12 ,  H04L7/0041

摘要： The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores.

摘要翻译： 本发明涉及一种能够建立核之间的通信的技术，其能够提供可在每个核心中设置的时钟频率的大的自由度，从而提供确定性的操作，小的通信延迟和高的可靠性。 本发明的目的是通过基于半导体器件内的通信历史分析影响半导体器件的性能的因素，并将分析反映到下一代半导体器件，来提供具有高可靠性的半导体器件。 改进的半导体器件包括用于与时钟信号clkA同步发送数据的核心A，用于接收与时钟信号clkB同步的数据的核心B与时钟信号clkA的上升或下降保持一致，并且 控制器用于控制核心A和核心B之间的通信。控制器以这样的方式进行控制，使得核心B可以仅接收在建立时钟信号clkB之前到达的数据。 控制器将历史记录存储在内核之间的通信状态。

公开(公告)号：US08081017B2

公开(公告)日：2011-12-20

申请号：US12515901

申请日：2007-11-09

申请人： Atsufumi Shibayama ,  Koichi Nose

发明人： Atsufumi Shibayama ,  Koichi Nose

IPC分类号： H03K21/00

CPC分类号： H03K23/48 ,  G06F1/08 ,  H03K23/667

摘要： To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

摘要翻译： 为了提供一种合理的分频电路，其中分频时钟信号的周期时间的变化小，在分频时钟信号和测试成本的最小周期时间很少的场合很多。 其分频比被指定为N / M的时钟信号分频电路都是N和M都是整数，包括选择三种情况之一的输出时钟选择电路（200）：输出输入时钟信号 输入时钟信号被反相输出，不输出输入时钟信号; 以及时钟选择控制电路（100），其产生用于控制输出时钟选择电路的上述选择的控制信号。 时钟选择控制电路在输入时钟信号的每个周期控制输出时钟选择电路的上述选择。

公开(公告)号：US20100052740A1

公开(公告)日：2010-03-04

申请号：US12515901

申请日：2007-11-09

申请人： Atsufumi Shibayama ,  Koichi Nose

发明人： Atsufumi Shibayama ,  Koichi Nose

IPC分类号： H03B19/00

CPC分类号： H03K23/48 ,  G06F1/08 ,  H03K23/667

摘要： To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

摘要翻译： 为了提供一种合理的分频电路，其中分频时钟信号的周期时间的变化小，在分频时钟信号和测试成本的最小周期时间很少的场合很多。 其分频比被指定为N / M的时钟信号分频电路均为N和Mare整数，包括选择三种情况之一的输出时钟选择电路（200）：输入时钟信号作为 输入时钟信号被反相输出，输入时钟信号不输出; 以及时钟选择控制电路（100），其生成用于控制输出时钟选择电路的上述选择的控制信号。 时钟选择控制电路在输入时钟信号的每个周期控制输出时钟选择电路的上述选择。