利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

39 条记录 (耗时 0.018 秒)

    Reduced processing in high-speed Reed-Solomon decoding
    1.
    发明授权
    Reduced processing in high-speed Reed-Solomon decoding 有权
    在高速Reed-Solomon解码中减少处理

    公开(公告)号：US08327241B2

    公开(公告)日：2012-12-04

    申请号：US12658597

    申请日：2010-02-10

    申请人： Yingquan Wu ,  Meng-Kun Lee ,  Kwok W. Yeung

    发明人： Yingquan Wu ,  Meng-Kun Lee ,  Kwok W. Yeung

    IPC分类号： H03M13/00

    CPC分类号： H03M13/153 ,  H03M13/1515 ,  H03M13/1585 ,  H03M13/6561

    摘要： Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift.

    摘要翻译： 公开了处理多项式。 同时执行与错误评估器多项式相关联的处理的至少一部分和与错误定位器多项式相关联的处理的至少一部分。 误差评估器多项式和误差定位多项式与Berlekamp-Massey处理相关联。 删除与错误评估器多项式相关联的数据，包括通过移位数组中的数据，使得数组中的至少一个元素在移位中清空。

    E/P durability by using a sub-range of a full programming range
    2.
    发明授权
    E/P durability by using a sub-range of a full programming range 有权
    使用完整编程范围的子范围的E / P耐久性

    公开(公告)号：US08400834B2

    公开(公告)日：2013-03-19

    申请号：US13295973

    申请日：2011-11-14

    申请人： Kwok W. Yeung ,  Meng-Kun Lee

    发明人： Kwok W. Yeung ,  Meng-Kun Lee

    IPC分类号： G11C16/06

    CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/344 ,  G11C16/349 ,  G11C2211/5621 ,  G11C2211/5646

    摘要： A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.

    摘要翻译： NAND闪速存储器控制器用于对包括NAND闪存芯片上的单元的NAND闪存芯片执行擦除操作; 该单元被配置为存储第一数量的位。 确定对NAND闪存芯片执行的擦除操作是否成功。 在确定对NAND闪存芯片执行的擦除操作不成功的情况下，由单元存储的比特数从第一比特数减少到第二比特数; 第二位数严格小于第一位数。

    E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE
    3.
    发明申请
    E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE 有权
    通过使用完整编程范围的子范围来实现E / P的可持续性

    公开(公告)号：US20120081971A1

    公开(公告)日：2012-04-05

    申请号：US13295973

    申请日：2011-11-14

    申请人： Kwok W. Yeung ,  Meng-Kun Lee

    发明人： Kwok W. Yeung ,  Meng-Kun Lee

    IPC分类号： G11C16/06

    CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/344 ,  G11C16/349 ,  G11C2211/5621 ,  G11C2211/5646

    摘要： A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.

    摘要翻译： NAND闪速存储器控制器用于对包括NAND闪存芯片上的单元的NAND闪存芯片执行擦除操作; 该单元被配置为存储第一数量的位。 确定对NAND闪存芯片执行的擦除操作是否成功。 在确定对NAND闪存芯片执行的擦除操作不成功的情况下，由单元存储的比特数从第一比特数减少到第二比特数; 第二位数严格小于第一位数。

    ECC with out of order completion
    4.
    发明授权
    ECC with out of order completion 有权
    ECC无序完成

    公开(公告)号：US08413009B2

    公开(公告)日：2013-04-02

    申请号：US13087290

    申请日：2011-04-14

    申请人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee

    发明人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1145 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/2957 ,  H03M13/4146 ,  H03M13/612

    摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

    摘要翻译： 公开了在纠错码（ECC）解码器中处理数据帧序列。 处理包括以数据帧序列接收第一数据帧，存储第一数据帧，通过ECC解码器发起第一数据帧的处理，从输入数据帧序列接收第二数据帧，存储第二数据帧 ，并且在通过ECC解码器处理完第一数据帧之前通过ECC解码器发起第二数据帧的处理。

    Hardware acceleration of DSP error recovery for flash memory
    5.
    发明授权
    Hardware acceleration of DSP error recovery for flash memory 有权
    闪存的DSP错误恢复的硬件加速

    公开(公告)号：US09142323B1

    公开(公告)日：2015-09-22

    申请号：US13408913

    申请日：2012-02-29

    申请人： Meng-Kun Lee ,  Kwok W. Yeung

    发明人： Meng-Kun Lee ,  Kwok W. Yeung

    IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C5/14

    CPC分类号： G11C29/42 ,  G06F11/1068 ,  G11C5/147 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418 ,  G11C29/52

    摘要： A method for correcting a cell voltage driftage in a NAND flash device is disclosed. An indicator indicating a cell voltage driftage in a memory unit of a NAND flash device is monitored by a processor. A cell voltage driftage in the NAND flash device is detected based at least in part on the indicator. One or more NAND commands correcting the cell voltage driftage are generated. The one or more NAND commands include a NAND command associated with changing a configuration setting of the NAND flash device.

    摘要翻译： 公开了一种用于校正NAND闪存器件中的电池电压漂移的方法。 指示NAND闪存装置的存储器单元中的单元电压漂移的指示器由处理器监视。 至少部分地基于指示符来检测NAND闪存器件中的电池电压漂移。 产生校正单元电压漂移的一个或多个NAND命令。 一个或多个NAND命令包括与改变NAND闪存器件的配置设置相关联的NAND命令。

    ECC with out of order completion
    6.
    发明授权
    ECC with out of order completion 有权
    ECC无序完成

    公开(公告)号：US08136008B1

    公开(公告)日：2012-03-13

    申请号：US13089794

    申请日：2011-04-19

    申请人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee ,  Kin Man Ng

    发明人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee ,  Kin Man Ng

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1145 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/2957 ,  H03M13/4146 ,  H03M13/612

    摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. The ECC decoder includes one or more stages and at least one of the stages is coupled to a memory configured to store data associated with the at least one stage.

    摘要翻译： 公开了在纠错码（ECC）解码器中处理数据帧序列。 处理包括接收数据帧序列中的第一数据帧，通过ECC解码器发起第一数据帧的处理，从输入的数据帧序列接收第二数据帧，以及通过ECC发起第二数据帧的处理 在通过ECC解码器处理完第一数据帧之前的解码器。 ECC解码器包括一个或多个阶段，并且至少一个级耦合到被配置为存储与至少一个级相关联的数据的存储器。

    E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE
    8.
    发明申请
    E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE 有权
    通过使用完整编程范围的子范围来实现E / P的可持续性

    公开(公告)号：US20110125959A1

    公开(公告)日：2011-05-26

    申请号：US13018152

    申请日：2011-01-31

    申请人： Kwok W. Yeung ,  Meng-Kun Lee

    发明人： Kwok W. Yeung ,  Meng-Kun Lee

    IPC分类号： G06F12/02

    CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/344 ,  G11C16/349 ,  G11C2211/5621 ,  G11C2211/5646

    摘要： A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.

    摘要翻译： 通过确定是否改变电压阈值的值来控制NAND快闪存储器系统。 电压阈值与对NAND闪存芯片的一部分的擦除操作相关联。 在确定改变电压阈值的值的情况下，改变电压阈值，并且存储电压阈值的变化值和与NAND闪速存储器芯片的部分相关联的标识符。

    ECC WITH OUT OF ORDER COMPLETION
    10.
    发明申请
    ECC WITH OUT OF ORDER COMPLETION 有权
    没有订单完成的ECC

    公开(公告)号：US20110239085A1

    公开(公告)日：2011-09-29

    申请号：US13087290

    申请日：2011-04-14

    申请人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee

    发明人： Kwok W. Yeung ,  Kin Ming Chan ,  Meng-Kun Lee

    IPC分类号： H03M13/00 ,  G06F11/08

    CPC分类号： H03M13/1145 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/2957 ,  H03M13/4146 ,  H03M13/612

    摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

    摘要翻译： 公开了在纠错码（ECC）解码器中处理数据帧序列。 处理包括以数据帧序列接收第一数据帧，存储第一数据帧，通过ECC解码器发起第一数据帧的处理，从输入数据帧序列接收第二数据帧，存储第二数据帧 ，并且在通过ECC解码器处理完第一数据帧之前通过ECC解码器发起第二数据帧的处理。