公开(公告)号：US20150249555A1

公开(公告)日：2015-09-03

申请号：US14244474

申请日：2014-04-03

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Freeman Y. Zhong ,  Ye Liu

IPC: H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/06

Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。

公开(公告)号：US09325537B2

公开(公告)日：2016-04-26

申请号：US14244474

申请日：2014-04-03

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Freeman Y. Zhong ,  Ye Liu

IPC: H04L27/08 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/06

Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。

公开(公告)号：US20150263848A1

公开(公告)日：2015-09-17

申请号：US14257315

申请日：2014-04-21

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Ye Liu

IPC: H04L7/00 ,  H03L7/08

CPC classification number: H03L7/0807 ,  H04L7/0004 ,  H04L7/033

Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.

Abstract translation: 描述的实施例在时钟和数据恢复（CDR）电路中提供使用校正积分累加器寄存器种子和换档重启的检测丢失采集和CDR重新启动。 在所描述的实施例中，如果针对不正确的采集轨迹的CDR电路，然后检测到CDR锁的实际丢失，并且通过校正积分累加器种子恢复CDR采集，则采用机制来引起更快的锁定状态丢失。