公开(公告)号：US11761996B2

公开(公告)日：2023-09-19

申请号：US17732824

申请日：2022-04-29

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R19/25 ,  H03K3/037 ,  G05F1/10

CPC classification number: G01R19/2513 ,  G05F1/10 ,  H03K3/037

Abstract: The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection. The apparatus connected to an integrated circuit power supply network comprises: a power supply voltage detector, comprising: N buffers, wherein an input terminal of a first buffer is connected to a clock signal, and output terminals of other buffers are connected to the input terminal of an adjacent buffer; N latch chains, each of which comprises M latches, wherein a clock input terminal of each latch is connected to a clock signal, a D terminal of a first latch of each latch chain is connected to the output terminal of a corresponding buffer, and Q terminals of other latches are connected to the D terminal of an adjacent latch, wherein M and N are positive integers, the VDD terminal of each latch is connected to an area in an integrated circuit power supply network where a power supply voltage is to be detected, and a grounding terminal of each latch is connected to a ground; and a voltage regulation module connected to the Q terminal of each latch and configured to detect data output of each latch to determine a magnitude of a power supply voltage.

公开(公告)号：US11983110B2

公开(公告)日：2024-05-14

申请号：US17850559

申请日：2022-06-27

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US20240256450A1

公开(公告)日：2024-08-01

申请号：US18633411

申请日：2024-04-11

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US12174232B2

公开(公告)日：2024-12-24

申请号：US17833884

申请日：2022-06-06

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R29/02 ,  H03K5/19 ,  H03K19/21

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

公开(公告)号：US20230004490A1

公开(公告)日：2023-01-05

申请号：US17850559

申请日：2022-06-27

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US20230003781A1

公开(公告)日：2023-01-05

申请号：US17833884

申请日：2022-06-06

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R29/02 ,  H03K5/19 ,  H03K19/21

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.