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公开(公告)号：US20220358078A1
公开(公告)日：2022-11-10
申请号：US17737527
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Junmou ZHANG , Chuang ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/42 , G06F13/40 , G06F15/173 , G06F9/30
Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.
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公开(公告)号：US20220357215A1
公开(公告)日：2022-11-10
申请号：US17736157
申请日：2022-05-04
Applicant: Lemon Inc.
Inventor： Chuang ZHANG , Shan LU , Junmou ZHANG , Yimin CHEN , Jian WANG , Yuanlin CHENG
Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.
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3.发明申请公开(公告)号：US20240378103A1
公开(公告)日：2024-11-14
申请号：US18660919
申请日：2024-05-10
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Pengjie DENG , Qi CHEN , Yimin CHEN , Shan LU , Jian WANG
Abstract: A bus anomaly detecting method, processing method, apparatus, system, device, and medium. The bus anomaly detecting method includes: at an interface for connecting a bus, activating a detection state in response to an access initiating apparatus sending an access request to an access receiving apparatus so as to, in the detection state, perform anomaly detection on response signal fed back by the access receiving apparatus for each access request, and block an interruption signal sent by the access initiating apparatus; in response to a response signal corresponding to an access request having an anomaly, terminating the detection state, recording bus anomaly information, and sending an interruption signal; and in a case where the response signal corresponding to each access request sent by the access initiating apparatus is received and has no anomaly, terminating the detection state to stop blocking the interruption signal sent by the access initiating apparatus.
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公开(公告)号：US20240305284A1
公开(公告)日：2024-09-12
申请号：US18597096
申请日：2024-03-06
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Junyan GUO , Mingming ZHANG , An ZHAO , Junmou ZHANG , Chuang ZHANG , Shan LU , Jian WANG
CPC classification number: H03K5/084 , H03K5/133 , H03K5/15033
Abstract: Embodiments of the present disclosure provide an apparatus and a method for generating a circuit clock signal. The apparatus comprises: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being respectively delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than that of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.
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公开(公告)号：US20220358071A1
公开(公告)日：2022-11-10
申请号：US17737415
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Chuang ZHANG , Junmou ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/40
Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240354368A1
公开(公告)日：2024-10-24
申请号：US18643872
申请日：2024-04-23
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Longfei BAI , Qi CHEN , Zhitao YANG , Zhilin XU , Yimin CHEN , Shan LU , Jian WANG
IPC: G06F17/16
CPC classification number: G06F17/16
Abstract: A method and a system for performing a matrix multiplication operator using a unit supporting convolution operator operation, an electronic device, and a non-transitory storage medium are provided. The method includes: transforming a first matrix of the matrix multiplication operator to an input data matrix of a convolution operator; transforming a second matrix of the matrix multiplication operator to a weight matrix of the convolution operator, matrix multiplication being performed on the first matrix and the second matrix; and performing a convolution operation on the input data matrix and the weight matrix, which are obtained through transforming, of the convolution operator using the unit supporting convolution operator operation to obtain an operation result of the matrix multiplication operator.
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公开(公告)号：US20240345620A1
公开(公告)日：2024-10-17
申请号：US18634421
申请日：2024-04-12
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Weifeng DONG , Jincai YE , Yuanlin CHENG , Pengfei LIU , Xinxia JIA , Shan LU , Jian WANG
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.
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公开(公告)号：US20240152474A1
公开(公告)日：2024-05-09
申请号：US18414920
申请日：2024-01-17
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Chuang ZHANG , Junmou ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/40
CPC classification number: G06F13/4027 , G06F2213/40
Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
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9.发明申请公开(公告)号：US20220357377A1
公开(公告)日：2022-11-10
申请号：US17732824
申请日：2022-04-29
Applicant: Lemon Inc.
Inventor： Junmou ZHANG , Dongrong ZHANG , Shan LU , Jian WANG
Abstract: The application provides an apparatus, a system, a detector and a method. The apparatus includes: a power supply voltage detector, including: N buffers, an input terminal of a first buffer being connected to a clock signal, output terminals of other buffers being connected to the input terminal of an adjacent buffer; N latch chains, each of which includes M latches, a clock input terminal of each latch being connected to a clock signal, a D terminal of a first latch of each latch chain being connected to the output terminal of a corresponding buffer, Q terminals of other latches being connected to the D terminal of an adjacent latch, M and N being positive integers, the D terminal of each latch being connected to an area where a power supply voltage is to be detected; and a voltage regulation module connected to the Q terminal of each latch.
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公开(公告)号：US20240168516A1
公开(公告)日：2024-05-23
申请号：US18513433
申请日：2023-11-17
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Jincai YE , Yuanlin CHENG , Shan LU , Jian WANG
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A clock synchronization method and apparatus, an electronic device and a storage medium are provided. The clock synchronization method includes: sending a trigger signal to a second processing module and recording a current count value of the first timer upon sending the trigger signal as a first count value; and reading a second count value from the second processing module, the second count value is a current count value of a second timer of the second processing module upon the second processing module receiving the trigger signal, and a count value of the second timer is used as a timing reference of the second processing module and sequentially increasing; the first count value and the second count value are used for a clock compensation to synchronize a first clock domain where the first processing module is located with a second clock domain where the second processing module is located.
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