公开(公告)号：US08058134B2

公开(公告)日：2011-11-15

申请号：US12618052

申请日：2009-11-13

申请人： Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

发明人： Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

摘要翻译： 退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。 第二个持续时间比第一个持续时间长。 退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

公开(公告)号：US20100210086A1

公开(公告)日：2010-08-19

申请号：US12618052

申请日：2009-11-13

申请人： Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

发明人： Li-Ting Wang ,  Keh-Chiang Ku ,  Yu-Chang Lin ,  Nai-Han Cheng ,  Li-Ping Huang

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

摘要翻译： 退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。 第二个持续时间比第一个持续时间长。 退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

公开(公告)号：US20070284615A1

公开(公告)日：2007-12-13

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/739

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US07741699B2

公开(公告)日：2010-06-22

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US20080242039A1

公开(公告)日：2008-10-02

申请号：US11690869

申请日：2007-03-26

申请人： Keh-Chiang Ku ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

发明人： Keh-Chiang Ku ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823878

摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

摘要翻译： 增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。 第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。

公开(公告)号：US20100105185A1

公开(公告)日：2010-04-29

申请号：US12259028

申请日：2008-10-27

申请人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

发明人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/28052 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28506 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

公开(公告)号：US07736968B2

公开(公告)日：2010-06-15

申请号：US12259028

申请日：2008-10-27

申请人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

发明人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/28052 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28506 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

公开(公告)号：US20080293204A1

公开(公告)日：2008-11-27

申请号：US11804927

申请日：2007-05-21

申请人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

发明人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6659

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅叠层; 将碳注入到半导体衬底中; 以及将n型杂质注入所述半导体衬底中以形成轻掺杂的源极/漏极（LDD）区域，其中所述n型杂质包含多于一个的磷原子。 n型杂质可以包括磷二聚体或磷酸四聚体。

公开(公告)号：US08212253B2

公开(公告)日：2012-07-03

申请号：US13228182

申请日：2011-09-08

申请人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

发明人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

IPC分类号： H01L29/167 ,  H01L29/26 ,  H01L29/24 ,  H01L21/22

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

摘要翻译： 半导体结构包括半导体衬底中的栅极堆叠和半导体衬底中的轻掺杂源极/漏极（LDD）区域。 LDD区域与栅堆叠下方的区域相邻。 LDD区域包含碳和n型杂质，n型杂质包括磷四聚体。

公开(公告)号：US20110316079A1

公开(公告)日：2011-12-29

申请号：US13228182

申请日：2011-09-08

申请人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

发明人： Chun-Feng Nieh ,  Keh-Chiang Ku ,  Nai-Han Cheng ,  Chi-Chun Chen ,  Li-Te S. Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

摘要翻译： 半导体结构包括半导体衬底中的栅极堆叠和半导体衬底中的轻掺杂源极/漏极（LDD）区域。 LDD区域与栅堆叠下方的区域相邻。 LDD区域包含碳和n型杂质，n型杂质包括磷四聚体。