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    Semiconductor devices and methods with bilayer dielectrics
    1.
    发明授权
    Semiconductor devices and methods with bilayer dielectrics 有权
    具有双层电介质的半导体器件和方法

    公开(公告)号：US07531399B2

    公开(公告)日：2009-05-12

    申请号：US11532308

    申请日：2006-09-15

    Applicant: Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    Inventor： Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    IPC: H01L21/8238

    CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/518

    Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

    Abstract translation: 公开了一种半导体器件，包括：衬底; 第一高k电介质层; 由不同的高k材料形成的第二高k电介质层; 和金属门。 在另一种形式中，公开了一种形成半导体器件的方法，包括：提供衬底; 在所述衬底上形成第一高k电介质层; 在所述第一介电层上形成不同高k材料的第二电介质层; 以及在所述第二电介质层上形成栅极结构。 在另一种形式中，公开了一种形成半导体器件的方法，其包括：提供衬底; 在基底上形成界面层; 在界面层上形成第一高k电介质层; 进行氮化技术; 进行退火; 在所述第一介电层上形成不同高k材料的第二高k电介质层; 以及在所述第二电介质层上方形成金属栅极结构。

    Ferroelectric materials and ferroelectric memory device made therefrom
    2.
    发明授权
    Ferroelectric materials and ferroelectric memory device made therefrom 有权
    铁电材料和由其制成的铁电存储器件

    公开(公告)号：US07307304B2

    公开(公告)日：2007-12-11

    申请号：US11150854

    申请日：2005-06-09

    Applicant: Tai-Bor Wu ,  Cheng-Lung Hung

    Inventor： Tai-Bor Wu ,  Cheng-Lung Hung

    IPC: H01L29/76

    CPC classification number: H01L21/02197 ,  H01L21/31691 ,  H01L28/55 ,  H01L29/516

    Abstract: A ferroelectric material includes a compound of formula (I): (Pb1−x−zBazAx)(ByZr1−y)O3,   (I) wherein 0≦x≦0.1, 0≦y≦0.020, 0.15≦z≦0.35, with the proviso that y≠0 when x=0, and that x≠0, when y=0; and wherein A is a first element having a valence number greater than that of Pb, and B is a second element having a valence number greater than that of Zr. A ferroelectric memory device made from the ferroelectric material is also disclosed.

    Abstract translation: 铁电材料包括式（I）的化合物：<？in-line-formula description =“In-line Formulas”end =“lead”→>（Pb 1-xz Ba （B）Z 1，Y 3，X 3，X 3，X 3， <？in-line-formula description =“In-line Formulas”end =“tail”？>其中0 <= x <= 0.1,0 <= y <= 0.020,0.15 <= z <= 0.35，附带条件 当x = 0时y <> 0，当y = 0时x <> 0; 并且其中A是具有大于Pb的价数的第一元素，B是具有大于Zr的价数的第二元素。 还公开了由铁电材料制成的铁电存储器件。

    Semiconductor devices and methods with bilayer dielectrics
    4.
    发明授权
    Semiconductor devices and methods with bilayer dielectrics 有权
    具有双层电介质的半导体器件和方法

    公开(公告)号：US08384159B2

    公开(公告)日：2013-02-26

    申请号：US12426477

    申请日：2009-04-20

    Applicant: Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    Inventor： Fong-Yu Yen ,  Cheng-Lung Hung ,  Peng-Fu Hsu ,  Vencent S. Chang ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/518

    Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

    Abstract translation: 公开了一种半导体器件，包括：衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层，所述第一高k材料选自HfO 2，HfSiO，HfSiON，HfTaO，HfTiO，HfTiTaO，HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层，所述第二高k材料不同于所述第一高k材料并选自HfO 2，HfSiO，HfSiON，HfTaO， HfTiO，HfTiTaO，HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。 第一电介质层包括选自N，O和Si的离子。

    Implantation method for reducing threshold voltage for high-K metal gate device
    5.
    发明授权
    Implantation method for reducing threshold voltage for high-K metal gate device 有权
    用于降低高K金属栅极器件的阈值电压的植入方法

    公开(公告)号：US07994051B2

    公开(公告)日：2011-08-09

    申请号：US12253741

    申请日：2008-10-17

    Applicant: Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

    Inventor： Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

    IPC: H01L21/00

    CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/268 ,  H01L21/32155 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成金属层，在金属层上形成半导体层，对金属层进行注入工艺 半导体层，使用包括F的物质的注入工艺，以及从包括高k电介质层，覆盖层，金属层和半导体层的多个层形成栅极结构。

    Sliding track for server chassis
    7.
    发明申请
    Sliding track for server chassis 审中-公开
    服务器机箱的滑轨

    公开(公告)号：US20060267465A1

    公开(公告)日：2006-11-30

    申请号：US11272144

    申请日：2005-11-14

    Applicant: Cheng-Lung Hung ,  Wei-Chen Huang

    Inventor： Cheng-Lung Hung ,  Wei-Chen Huang

    IPC: A47B81/00

    CPC classification number: G06F1/183 ,  A47B88/483 ,  H05K7/1489

    Abstract: A sliding track for a server chassis includes a first member and a second member. The first member and the second member are movable relative to each other through an anchor member, sliding in a guiding slot. The first member has a flange extended respectively from two ends so that when the second member is sliding relative to the first member, two ends of the second member are sliding on the flanges.

    Abstract translation: 用于服务器机架的滑轨包括第一构件和第二构件。 第一构件和第二构件可以通过锚定构件相对于彼此移动，在引导狭槽中滑动。 第一构件具有分别从两端延伸的凸缘，使得当第二构件相对于第一构件滑动时，第二构件的两端在凸缘上滑动。

    Electrical connector with light emitting device
    8.
    发明授权
    Electrical connector with light emitting device 失效
    带有发光装置的电气连接器

    公开(公告)号：US06663417B1

    公开(公告)日：2003-12-16

    申请号：US10247485

    申请日：2002-09-20

    Applicant: Cheng-Lung Hung

    Inventor： Cheng-Lung Hung

    IPC: H01R300

    CPC classification number: H01R13/6641 ,  H01R13/7175 ,  H01R24/64

    Abstract: An electrical connector with light emitting device. The electrical connector includes a casing, an insulative housing disposed inside the casing. A light emitting device and a light transmitting element are disposed on top of the insulative housing. The insulative housing includes two slots disposed on top of the insulative housing. A groove is disposed on a distal front end of each of the slots. The light emitting device is fitted into the slot above the insulative housing so that a certain distance is maintained between the light emitting device in the slot and the light transmitting element. The casing covers the outer part of the insulative housing, the light transmitting device, and the light transmitting element wherein at least a front side of the insulative housing and a front side of the transmitting element are exposed.

    Abstract translation: 具有发光装置的电连接器。 电连接器包括壳体，设置在壳体内部的绝缘壳体。 发光器件和透光元件设置在绝缘壳体的顶部。 绝缘壳体包括设置在绝缘壳体顶部的两个槽。 在每个狭槽的远端前端设置有凹槽。 发光装置装配在绝缘壳体上方的狭槽中，使得狭槽内的发光装置与光传输元件之间保持一定距离。 壳体覆盖绝缘壳体的外部部分，透光装置和透光元件，其中绝缘壳体的至少前侧和透射元件的前侧暴露。

    Integrated circuit metal gate structure and method of fabrication
    9.
    发明授权
    Integrated circuit metal gate structure and method of fabrication 有权
    集成电路金属栅极结构及其制造方法

    公开(公告)号：US08679962B2

    公开(公告)日：2014-03-25

    申请号：US12264822

    申请日：2008-11-04

    Applicant: Yong-Tian Hou ,  Chien-Hao Chen ,  Donald Y. Chao ,  Cheng-Lung Hung

    Inventor： Yong-Tian Hou ,  Chien-Hao Chen ,  Donald Y. Chao ,  Cheng-Lung Hung

    IPC: H01L21/3205

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.

    Abstract translation: 提供一种形成栅极结构的方法。 该方法包括在栅极结构中提供金属层，金属层包括吸氧组合物。 金属层从界面层吸收氧气，这可能会降低界面层的厚度。 吸收的氧将金属层转化为金属氧化物，其可以用作栅极结构的栅极电介质。 还提供了多层金属栅极结构，其包括吸氧过程金属层，含氧金属层和覆盖在高k栅极电介质上的多晶硅界面金属层。

    High-k metal gate device
    10.
    发明授权
    High-k metal gate device 有权
    高k金属门装置

    公开(公告)号：US08258546B2

    公开(公告)日：2012-09-04

    申请号：US13186656

    申请日：2011-07-20

    Applicant: Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

    Inventor： Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

    IPC: H01L27/118

    CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/268 ,  H01L21/32155 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

    Abstract translation: 半导体器件包括半导体衬底和形成在衬底中的晶体管，晶体管具有栅极堆叠，其具有形成在衬底上的界面层，形成在界面层上的高k电介质层，在高层上形成的金属层 - 介电层，在界面层和高k电介质层之间形成的覆盖层; 以及形成在所述金属层上的掺杂层，所述掺杂层至少包括F.

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