公开(公告)号：US09401371B1

公开(公告)日：2016-07-26

申请号：US14863633

申请日：2015-09-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Chiajung Chiu

IPC: H01L21/336 ,  H01L29/76 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/764 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/768 ,  H01L27/11565

Abstract: A method for manufacturing a memory device, which can be configured as a 3D NAND flash memory, and includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

Abstract translation: 一种用于制造可被配置为3D NAND闪速存储器的存储器件的方法，并且包括多个堆叠的导电条，包括偶数堆叠和具有侧壁的奇数堆叠。 堆叠中的一些导电条被配置为字线。 数据存储结构设置在偶数和奇数堆栈的侧壁上。 在相应的偶数和奇数个导体条之间的有源支柱包括连接在堆叠之间的沟槽底部的偶数和奇数半导体膜，并具有外表面和内表面。 外表面接触形成存储器单元的3D阵列的对应偶数和奇数堆叠的侧壁上的数据存储结构; 内表面由可以包括间隙的绝缘结构隔开。 半导体膜可以是具有U形电流路径的薄膜。

公开(公告)号：US09379126B2

公开(公告)日：2016-06-28

申请号：US13935375

申请日：2013-07-03

Applicant: Macronix International Co., Ltd.

Inventor： Chiajung Chiu ,  Guanru Lee

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11578

Abstract: A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure.

Abstract translation: 形成导体结构的方法可导致垂直侧壁。 该方法在多个间隔开的有源层堆叠中沉积衬里。 隔离材料形成在衬里之上，在间隔开的堆叠之间和之间。 隔离材料中的多个沟槽布置成跨过多个间隔开的活性条带堆叠，留下至少一个衬垫的残留物在沟槽的底部之间的活动条的堆叠之间并且在 间隔开的活动条带。 选择性地去除沟槽底部的衬里的残留物和间隔开的有源层堆叠的侧壁。 然后，多个沟槽用导电或半导体材料填充以形成镶嵌结构。