公开(公告)号：US09123778B2

公开(公告)日：2015-09-01

申请号：US13897702

申请日：2013-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Guanru Lee

IPC: H01L21/4763 ,  H01L21/8242 ,  H01L29/40 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L21/76808 ,  H01L21/28282 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract translation: 对于某些三维堆叠的存储器件，用于存储器单元的位线或字线被堆叠成布置成沿第一方向延伸的间隔开的脊状结构。 在这种结构中，互补字线或位线可以是间隔开的镶嵌特征。 镶嵌导体可以使用双图案化掩模形成，以蚀刻次光刻牺牲线，在牺牲线上形成填充物，然后去除牺牲线以留下充当填充物中镶嵌模具的沟槽。 然后用导体材料填充沟槽。 3D存储器阵列可以包括具有高K阻挡介电层的介电电荷俘获存储器单元，并且其中导体材料包括高功函数材料。

公开(公告)号：US09379126B2

公开(公告)日：2016-06-28

申请号：US13935375

申请日：2013-07-03

Applicant: Macronix International Co., Ltd.

Inventor： Chiajung Chiu ,  Guanru Lee

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11578

Abstract: A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure.

Abstract translation: 形成导体结构的方法可导致垂直侧壁。 该方法在多个间隔开的有源层堆叠中沉积衬里。 隔离材料形成在衬里之上，在间隔开的堆叠之间和之间。 隔离材料中的多个沟槽布置成跨过多个间隔开的活性条带堆叠，留下至少一个衬垫的残留物在沟槽的底部之间的活动条的堆叠之间并且在 间隔开的活动条带。 选择性地去除沟槽底部的衬里的残留物和间隔开的有源层堆叠的侧壁。 然后，多个沟槽用导电或半导体材料填充以形成镶嵌结构。

公开(公告)号：US09397113B2

公开(公告)日：2016-07-19

申请号：US14581064

申请日：2014-12-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guanru Lee

IPC: H01L29/76 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked NAND strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical columns in the plurality of vertical columns are gates to only one side of the first side and the second side of the opposite sides of the vertically stacked semiconductor strips. The vertical columns in the plurality of vertical columns are gates to adjacent stacks in the plurality of vertically stacked NAND strings.

Abstract translation: 垂直栅极非易失性NAND阵列包括多个垂直堆叠的NAND串的非易失性存储单元，多个垂直堆叠的NAND串正交布置的多个字线以及电耦合到多个垂直堆叠的多个垂直列的导电栅极材料 的字线。 多个垂直堆叠的NAND串具有包括第一侧和第二侧的相对侧的垂直堆叠的半导体条。 多个垂直列中的垂直列是仅垂直堆叠的半导体条的相对侧的第一侧和第二侧的一侧的栅极。 多个垂直列中的垂直列是多个垂直堆叠的NAND串中的相邻堆栈的栅极。

公开(公告)号：US09105667B2

公开(公告)日：2015-08-11

申请号：US13928002

申请日：2013-06-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guanru Lee

IPC: H01L29/00 ,  H01L29/792 ,  H01L29/66 ,  H01L29/04 ,  H01L27/108 ,  H01L29/423 ,  H01L21/311 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/31144 ,  H01L27/10876 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/4236 ,  H01L29/66621

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed over the first semiconductor layer and includes a recess in a vertical direction towards the first semiconductor layer. The third semiconductor layer is formed in the recess of the second semiconductor layer and includes a seam or void in the recess.

Abstract translation: 半导体器件包括第一半导体层，第二半导体层和第三半导体层。 第二半导体层形成在第一半导体层之上，并且包括在朝向第一半导体层的垂直方向上的凹部。 第三半导体层形成在第二半导体层的凹部中并且在凹部中包括接缝或空隙。