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公开(公告)号：US12224756B2
公开(公告)日：2025-02-11
申请号：US18103472
申请日：2023-01-30
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Shih-Che Hung , Tse-Hsien Yeh
Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.
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公开(公告)号：US12003245B2
公开(公告)日：2024-06-04
申请号：US17902917
申请日：2022-09-05
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04B1/7073 , H04L7/00 , H04L7/033 , H04L27/227
CPC classification number: H03L7/0807 , H03L7/085 , H04B1/7073 , H04L7/0025 , H04L7/0331 , H04L27/2271 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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Patent Agency Ranking
公开(公告)号：US11349485B2
公开(公告)日：2022-05-31
申请号：US16744188
申请日：2020-01-16
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Tse-Hsien Yeh , Shih-Che Hung
Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
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4.发明公开公开(公告)号：US20240007110A1
公开(公告)日：2024-01-04
申请号：US18103472
申请日：2023-01-30
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Shih-Che Hung , Tse-Hsien Yeh
CPC classification number: H03L7/0807 , G06N3/063 , H03L7/093
Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.
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公开(公告)号：US20230163765A1
公开(公告)日：2023-05-25
申请号：US17902917
申请日：2022-09-05
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04L7/033 , H04L7/00 , H04B1/7073
CPC classification number: H03L7/0807 , H03L7/085 , H04L7/0331 , H04L7/0025 , H04B1/7073 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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公开(公告)号：US20240283458A1
公开(公告)日：2024-08-22
申请号：US18648493
申请日：2024-04-29
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Yi-Hsien Cho
IPC: H03L7/08 , H03L7/085 , H04B1/7073 , H04L7/00 , H04L7/033 , H04L27/227
CPC classification number: H03L7/0807 , H03L7/085 , H04B1/7073 , H04L7/0025 , H04L7/0331 , H04L27/2271 , H04B2201/7073
Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.
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公开(公告)号：US20200244272A1
公开(公告)日：2020-07-30
申请号：US16744188
申请日：2020-01-16
Applicant: MEDIATEK INC.
Inventor： Chien-Kai Kao , Tse-Hsien Yeh , Shih-Che Hung
Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
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