公开(公告)号：US20250077429A1

公开(公告)日：2025-03-06

申请号：US18950269

申请日：2024-11-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yaniv Strassberg ,  Guy Harel ,  Gabi Liron ,  Yuval Itkin

IPC: G06F12/0815 ,  G06F12/084 ,  G06F12/14

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

公开(公告)号：US11836083B2

公开(公告)日：2023-12-05

申请号：US17536141

申请日：2021-11-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Avraham Koren ,  Ariel Shahar ,  Liran Liss ,  Gabi Liron ,  Aviad Shaul Yehezkel

IPC: G06F12/0882 ,  G06F13/16 ,  G06F12/0831

CPC classification number: G06F12/0882 ,  G06F12/0833 ,  G06F12/0835 ,  G06F13/1673

Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

公开(公告)号：US12216580B1

公开(公告)日：2025-02-04

申请号：US18456536

申请日：2023-08-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yaniv Strassberg ,  Guy Harel ,  Gabi Liron ,  Yuval Itkin

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/14

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

公开(公告)号：US20230133439A1

公开(公告)日：2023-05-04

申请号：US17536141

申请日：2021-11-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Avraham Koren ,  Ariel Shahar ,  Liran Liss ,  Gabi Liron ,  Aviad Shaul Yehezkel

IPC: G06F12/0882 ,  G06F12/0831 ,  G06F13/16

Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

公开(公告)号：US20160294983A1

公开(公告)日：2016-10-06

申请号：US14672397

申请日：2015-03-30

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Yevgeny Kliteynik ,  Aviad Yehezkel ,  Liran Liss ,  Amir Vadai ,  Eli Cohen ,  Erez Shitrit ,  Gabi Liron

IPC: H04L29/06 ,  G06F15/173 ,  G06F12/10

CPC classification number: G06F15/17331 ,  G06F12/0802

Abstract: A method for data storage includes provisioning, in a cluster of computers, including at least first and second computers, which are connected to a packet data network, a range of RAM on the second computer for use by the first computer. Blocks of data are stored in the provisioned range for use by programs running on the first computer. Upon incurring a page fault on the first computer in response to a request for a page of virtual memory by a program running on the first computer, a block swap request is directed to the NIC of the first computer with respect to the requested page. In response to the block swap request, an RDMA read request is initiated by the NIC via the network to the NIC of the second computer, to retrieve the requested page from the provisioned range, so as to resolve the page fault.

Abstract translation: 一种用于数据存储的方法包括在计算机集群中提供包括连接到分组数据网络的至少第一和第二计算机，第二计算机上的RAM的范围供第一计算机使用。 数据块存储在供应范围内供第一台计算机上运行的程序使用。 响应于通过在第一计算机上运行的程序对虚拟存储器页的请求而在第一计算机上引起页错误时，块交换请求针对所请求的页面被引导到第一计算机的NIC。 响应于块交换请求，NIC通过网络发起RDMA读取请求到第二台计算机的NIC，从提供的范围中检索所请求的页面，以便解决页面错误。