公开(公告)号：US12216580B1

公开(公告)日：2025-02-04

申请号：US18456536

申请日：2023-08-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yaniv Strassberg ,  Guy Harel ,  Gabi Liron ,  Yuval Itkin

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/14

Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

公开(公告)号：US20240205021A1

公开(公告)日：2024-06-20

申请号：US18497000

申请日：2023-10-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Nir Eilam ,  Yuval Itkin ,  Haim Kupershmidt ,  Yigal Edery ,  Uriya Stern ,  Boaz Shahar ,  Mor Sfadia

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3247 ,  H04L9/0825 ,  H04L9/3263

Abstract: In one embodiment, a device includes a memory to store a first public key indicating security ownership of the device by a first owner, an interface to receive a signature of an intermediate public key signed by a first owner signing service with a first private key, and processing circuitry to load the intermediate public key in the memory, responsively to authenticating the signature, and remove the first public key from the memory, and wherein the interface is to receive a second public key and a signature of the second public key signed by a second owner signing service with an intermediate private key, the processing circuitry is to load a second public key in the memory indicating ownership has been transferred to the second owner responsively to authenticating the signature of the second public key with the intermediate public key, and remove the intermediate public key from the memory.

公开(公告)号：US11741232B2

公开(公告)日：2023-08-29

申请号：US17163599

申请日：2021-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

CPC classification number: G06F21/572 ,  G06F8/65 ,  G06F9/445 ,  G06F2221/033

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US11762747B2

公开(公告)日：2023-09-19

申请号：US17003437

申请日：2020-08-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin

IPC: G06F11/00 ,  G06F11/22 ,  G06F9/4401 ,  H04L43/50 ,  G06F21/60 ,  G06F13/40 ,  G06F11/273

CPC classification number: G06F11/2294 ,  G06F9/4401 ,  G06F11/22 ,  G06F13/4063 ,  G06F21/606 ,  H04L43/50 ,  G06F11/2733

Abstract: A compute node includes a network-connected device, and a baseboard management controller (BMC) that is connected to the network-connected device by a sideband interface. The network-connected device is configured to communicate with a network. The BMC is configured to configure the network-connected device, via the sideband interface, to engage in a debug session over the network with a remote debug device.

公开(公告)号：US20220245251A1

公开(公告)日：2022-08-04

申请号：US17163599

申请日：2021-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US20220075737A1

公开(公告)日：2022-03-10

申请号：US17013693

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Itkin ,  Yaniv Strassberg ,  Guy Harel ,  Ahmad Atamlh

IPC: G06F12/14 ,  G06F12/02 ,  G06F12/0891 ,  G06F21/79

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

公开(公告)号：US10587535B2

公开(公告)日：2020-03-10

申请号：US16416224

申请日：2019-05-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Itkin

IPC: G06F9/455 ,  H04L12/937 ,  G06F9/4401 ,  H04L12/931 ,  H04L12/935

Abstract: A host computer is linked to a network interface controller having a plurality of network ports connectable to a data network. The network interface controller has an embedded central processing unit, a host interface linked to the host central processing unit, a sideband interface and a baseboard management controller linked to the network interface controller via the sideband interface. The baseboard management controller connects to a management network via the management network port. The embedded central processing unit in the network interface controller is linked to a datacenter manager via the management network port of the baseboard management controller, enabling the datacenter manager to instruct the embedded central processing unit to control data flows in the network interface controller between the host interface and the data network.

公开(公告)号：US10445279B1

公开(公告)日：2019-10-15

申请号：US16039386

申请日：2018-07-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin ,  Assad Khamaisee

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42

Abstract: A computer system includes a system bus having multiple lanes, one or more peripheral devices, and a bus controller. The peripheral devices are coupled to the system bus. The bus controller is configured to receive, from one or more of the peripheral devices, respective indications of numbers of the lanes requested by the peripheral devices, and to configure the system bus in response to the indications.

公开(公告)号：US20180181410A1

公开(公告)日：2018-06-28

申请号：US15391886

申请日：2016-12-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin ,  Ran Sofer ,  Amir Ancel ,  Ido Gross

IPC: G06F9/44 ,  G06F13/42 ,  G06F1/24

CPC classification number: G06F9/4411 ,  G06F1/24 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A startup sequence in a computer system is initiated by detecting a bus reset event in an I/O device connected to a host, and responsively to the bus reset event communicating resources required to be allocated by the host. When a startup command from a host driver is not received within a predetermined bus reset count, the device autonomously changes its current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration. The safe mode configuration is communicated from the device to the host.

公开(公告)号：US09985820B2

公开(公告)日：2018-05-29

申请号：US14700206

申请日：2015-04-30

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Yuval Itkin

IPC: G06F15/173 ,  H04L12/24 ,  H04L29/12 ,  H04L12/741

CPC classification number: H04L41/04 ,  H04L43/0817 ,  H04L45/74 ,  H04L61/2015 ,  H04L61/2038 ,  H04L61/6022

Abstract: A network adapter includes one or more ports and circuitry. The ports are configured to connect to a communication network. The circuitry is coupled to a network node that includes multiple hosts, and is configured to exchange management packets between a control server and a Baseboard Management Controller (BMC) that runs at least first and second BMC instances that are assigned respective different first and second IP addresses or MAC addresses and are associated respectively with first and second hosts, and to exchange, over the communication network via the one or more ports, data packets between the hosts and one or more remote nodes.