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    Combined power and input/output line
    2.
    发明授权
    Combined power and input/output line 有权
    组合电源和输入/输出线

    公开(公告)号：US08898356B2

    公开(公告)日：2014-11-25

    申请号：US13841439

    申请日：2013-03-15

    Applicant: Microchip Technology Incorporated

    Inventor： Joseph Julicher ,  Pieter Schieke ,  Vivien Delport

    IPC: G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  G06F13/10

    CPC classification number: G06F13/10 ,  G06F1/266 ,  G06F13/4072 ,  G06F13/4291 ,  H04B3/542 ,  H04B3/548

    Abstract: An electronic device including a host system including a source; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.

    Abstract translation: 一种电子设备，包括：包括源的主机系统; 以及经由组合电力I / O线可操作地耦合到所述主机系统的目标系统; 其中所述目标系统包括传输晶体管和开关系统协作以允许所述源以第一模式经由所述组合功率I / O线对所述目标系统上的电源电容器充电，并且在所述第一模式期间交替地对所述电源电容器进行充电和放电 在第二模式中通过组合电源I / O线进行通信，其中交替充电和放电与所述通信同步。

    Randomizing Current Injection Circuit to Obscure Gate Noise for Added Security
    6.
    发明申请
    Randomizing Current Injection Circuit to Obscure Gate Noise for Added Security 有权
    随机化电流注入电路以掩盖增加门禁噪声的安全性

    公开(公告)号：US20140270169A1

    公开(公告)日：2014-09-18

    申请号：US14207902

    申请日：2014-03-13

    Applicant: Microchip Technology Incorporated

    Inventor： Vivien Delport

    IPC: H04L9/14

    CPC classification number: H04L9/14 ,  H04L9/003 ,  H04L2209/12

    Abstract: A circuit for obscuring gate switching noise includes a synchronous clock source; an asynchronous clock source; at least one current source; and a random number generating circuit for receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals for controlling the current source.

    Abstract translation: 用于遮蔽门开关噪声的电路包括同步时钟源; 异步时钟源; 至少一个电流源; 以及随机数产生电路，用于从同步时钟源和异步时钟源接收时钟输入，该随机数产生电路产生用于控制电流源的随机改变的异步数字控制信号。

    ENHANCED MICROPROCESSOR OR MICROCONTROLLER
    7.
    发明申请
    ENHANCED MICROPROCESSOR OR MICROCONTROLLER 审中-公开
    增强微处理器或MICROCONTROLLER

    公开(公告)号：US20140019991A1

    公开(公告)日：2014-01-16

    申请号：US14028458

    申请日：2013-09-16

    Applicant: Microchip Technology Incorporated

    Inventor： Joseph Julicher ,  Zacharias Marthinus Smit ,  Sean Steedman ,  Vivien Delport ,  Jerrold S. Zdenek ,  Ryan Scott Ellison ,  Eric Schroeder

    IPC: G06F9/46

    CPC classification number: G06F9/461

    Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

    Abstract translation: 微控制器设备具有中央处理单元（CPU）; 与分配到多个存储体中的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体状态 寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时 从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

    Randomizing current injection circuit to obscure gate noise for added security
    9.
    发明授权
    Randomizing current injection circuit to obscure gate noise for added security 有权
    随机化电流注入电路以掩盖门噪声，增加安全性

    公开(公告)号：US09306746B2

    公开(公告)日：2016-04-05

    申请号：US14207902

    申请日：2014-03-13

    Applicant: Microchip Technology Incorporated

    Inventor： Vivien Delport

    IPC: H04L29/06 ,  H04L9/14 ,  H04L9/00

    CPC classification number: H04L9/14 ,  H04L9/003 ,  H04L2209/12

    Abstract: A circuit for obscuring gate switching noise includes a synchronous clock source; an asynchronous clock source; at least one current source; and a random number generating circuit for receiving clock inputs from the synchronous clock source and the asynchronous clock source, the random number generating circuit generating randomly changing asynchronous digital control signals for controlling the current source.

    Abstract translation: 用于遮蔽门开关噪声的电路包括同步时钟源; 异步时钟源; 至少一个电流源; 以及随机数产生电路，用于从同步时钟源和异步时钟源接收时钟输入，该随机数产生电路产生用于控制电流源的随机改变的异步数字控制信号。

    Combined Power and Input/Output Line
    10.
    发明申请
    Combined Power and Input/Output Line 有权
    组合电源和输入/输出线

    公开(公告)号：US20140281049A1

    公开(公告)日：2014-09-18

    申请号：US13841439

    申请日：2013-03-15

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Joseph Julicher ,  Pieter Schieke ,  Vivien Delport

    IPC: G06F13/10

    CPC classification number: G06F13/10 ,  G06F1/266 ,  G06F13/4072 ,  G06F13/4291 ,  H04B3/542 ,  H04B3/548

    Abstract: An electronic device including a host system including a source; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.

    Abstract translation: 一种电子设备，包括：包括源的主机系统; 以及经由组合电力I / O线可操作地耦合到所述主机系统的目标系统; 其中所述目标系统包括传输晶体管和开关系统协作以允许所述源以第一模式经由所述组合功率I / O线对所述目标系统上的电源电容器充电，并且在所述第一模式期间交替地对所述电源电容器进行充电和放电 在第二模式中通过组合电源I / O线进行通信，其中交替充电和放电与所述通信同步。

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