公开(公告)号：US20210174859A1

公开(公告)日：2021-06-10

申请号：US16706548

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C11/4076 ,  H01L25/065

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US11670358B2

公开(公告)日：2023-06-06

申请号：US17496728

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C7/00 ,  G11C11/4076 ,  H01L25/065

CPC classification number: G11C11/4076 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US20220028443A1

公开(公告)日：2022-01-27

申请号：US17496728

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C11/4076 ,  H01L25/065

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US20240311231A1

公开(公告)日：2024-09-19

申请号：US18525395

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/10 ,  G06F12/0292 ,  G06F2212/1032

Abstract: An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.

公开(公告)号：US20210175208A1

公开(公告)日：2021-06-10

申请号：US16706642

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

公开(公告)号：US20240311238A1

公开(公告)日：2024-09-19

申请号：US18525354

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F11/16 ,  G11C8/08 ,  G11C17/16

CPC classification number: G06F11/1068 ,  G06F11/1654 ,  G11C8/08 ,  G11C17/16

Abstract: An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.

公开(公告)号：US20210173773A1

公开(公告)日：2021-06-10

申请号：US16706635

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F12/06 ,  G06F11/07 ,  H01L25/065 ,  G11C11/407

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US20240126692A1

公开(公告)日：2024-04-18

申请号：US18396638

申请日：2023-12-26

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F12/06 ,  G06F11/07 ,  G11C11/407 ,  G11C29/04 ,  H01L25/065

CPC classification number: G06F12/0646 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0793 ,  G11C11/407 ,  G11C29/04 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US11868252B2

公开(公告)日：2024-01-09

申请号：US16706635

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F11/07 ,  G06F12/06 ,  H01L25/065 ,  G11C11/407 ,  G11C29/04

CPC classification number: G06F12/0646 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0793 ,  G11C11/407 ,  G11C29/04 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US11145352B2

公开(公告)日：2021-10-12

申请号：US16706548

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C7/00 ,  G11C11/4076 ,  H01L25/065

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.