公开(公告)号：US12276686B2

公开(公告)日：2025-04-15

申请号：US17894227

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G01R27/08 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

公开(公告)号：US20210201993A1

公开(公告)日：2021-07-01

申请号：US17011018

申请日：2020-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

公开(公告)号：US11087851B2

公开(公告)日：2021-08-10

申请号：US16895025

申请日：2020-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhengyi Zhang ,  Dan Xu ,  Tomoko Ogura Iwasaki

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

公开(公告)号：US20220404408A1

公开(公告)日：2022-12-22

申请号：US17894227

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G11C16/08 ,  G11C16/04 ,  G01R27/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

公开(公告)号：US12183396B2

公开(公告)日：2024-12-31

申请号：US18096072

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

公开(公告)号：US11557341B2

公开(公告)日：2023-01-17

申请号：US17011018

申请日：2020-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

公开(公告)号：US11538535B2

公开(公告)日：2022-12-27

申请号：US17443370

申请日：2021-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhengyi Zhang ,  Dan Xu ,  Tomoko Ogura Iwasaki

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

公开(公告)号：US20210202013A1

公开(公告)日：2021-07-01

申请号：US16895025

申请日：2020-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhengyi Zhang ,  Dan Xu ,  Tomoko Ogura Iwasaki

IPC: G11C16/28 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/04

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

公开(公告)号：US20210199703A1

公开(公告)日：2021-07-01

申请号：US16877710

申请日：2020-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G01R27/08 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.

公开(公告)号：US20240393977A1

公开(公告)日：2024-11-28

申请号：US18636584

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Ratna Priyanka Sistla ,  Dan Xu ,  Tomoko Ogura Iwasaki ,  Caixia Yang ,  Lee-eun Yu

IPC: G06F3/06

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.