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    Over-limit electrical condition protection circuits for integrated circuits
    4.
    发明授权
    Over-limit electrical condition protection circuits for integrated circuits 有权

    公开(公告)号：US09705318B2

    公开(公告)日：2017-07-11

    申请号：US14246309

    申请日：2014-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Michael Chaine ,  Xiaofeng Fan

    IPC: H02H9/04 ,  H01L27/02 ,  H01L29/74

    CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L29/7436

    Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

    Over-limit electrical condition protection circuits and methods
    5.
    发明授权
    Over-limit electrical condition protection circuits and methods 有权
    超限电气保护电路及方法

    公开(公告)号：US09490631B2

    公开(公告)日：2016-11-08

    申请号：US14275211

    申请日：2014-05-12

    Applicant: Micron Technology, Inc.

    Inventor： Xiaofeng Fan ,  Michael Chaine ,  John David Porter

    IPC: H02H3/22 ,  H02H9/04 ,  H01L27/02 ,  H05K1/02

    CPC classification number: H02H9/044 ,  H01L27/0248 ,  H01L27/0251 ,  H02H9/046 ,  H05K1/0259

    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

    Abstract translation: 公开了用于保护电路免受过电压条件的设备和方法。 一个示例性设备包括耦合到要保护的电路的保护电路。 要保护的电路耦合到焊盘节点。 保护电路被配置为将电流从焊盘节点传导到参考电压节点，以保护电路免受超限电气状况的影响。 保护电路具有耦合到焊盘节点的触发电路，并被配置为响应于提供给具有超过触发电压的电压的焊盘节点的电压，触发分流电路以将电流从焊盘节点传导到参考电压节点。 在一些实施例中，触发电路与被保护的电路相匹配。

    PIXEL ARRAY WITH SHARED PIXELS IN A SINGLE COLUMN AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS
    6.
    发明申请
    PIXEL ARRAY WITH SHARED PIXELS IN A SINGLE COLUMN AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS 有权
    具有共享像素的像素阵列在单列和相关设备，系统和方法

    公开(公告)号：US20160088250A1

    公开(公告)日：2016-03-24

    申请号：US14961037

    申请日：2015-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Zhiping Yin ,  Xiaofeng Fan ,  Xiangli Li

    IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/357

    CPC classification number: H04N5/3745 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14645 ,  H04N5/3575

    Abstract: Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region.

    Abstract translation: 单列中具有共享像素的像素阵列以及相关联的设备，系统和方法在此公开。 在一个实施例中，像素阵列包括浮动扩散区域，源极跟随器晶体管，源极跟随器晶体管，其具有耦合到浮置扩散区域的栅极，与第一颜色相关联的多个第一像素，以及与第二颜色相关联的多个第二像素 颜色与第一颜色不同，并且排列在具有第一像素的单列中。 第一和第二像素配置成将电荷转移到浮动扩散区。

    OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS
    7.
    发明申请
    OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS 有权
    超限电气保护电路及方法

    公开(公告)号：US20140240883A1

    公开(公告)日：2014-08-28

    申请号：US14275211

    申请日：2014-05-12

    Applicant: Micron Technology, Inc.

    Inventor： Xiaofeng Fan ,  Michael Chaine ,  John David Porter

    IPC: H02H9/04

    CPC classification number: H02H9/044 ,  H01L27/0248 ,  H01L27/0251 ,  H02H9/046 ,  H05K1/0259

    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

    Abstract translation: 公开了用于保护电路免受过电压条件的设备和方法。 一个示例性设备包括耦合到要保护的电路的保护电路。 要保护的电路耦合到焊盘节点。 保护电路被配置为将电流从焊盘节点传导到参考电压节点，以保护电路免受超限电气状况的影响。 保护电路具有耦合到焊盘节点的触发电路，并被配置为响应于提供给具有超过触发电压的电压的焊盘节点的电压，触发分流电路以将电流从焊盘节点传导到参考电压节点。 在一些实施例中，触发电路与被保护的电路相匹配。

    OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS
    8.
    发明申请
    OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS 有权
    用于集成电路的超限电气保护电路

    公开(公告)号：US20140218830A1

    公开(公告)日：2014-08-07

    申请号：US14246309

    申请日：2014-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Michael Chaine ,  Xiaofeng Fan

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L29/7436

    Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

    Abstract translation: 提供了用于保护集成电路免受超限电气条件的保护电路和方法。 一个示例包括具有形成在隔离掺杂阱区中的至少一部分并且被配置为响应于超过触发条件的输入而切换到低阻抗状态并且还具有耦合到参考电压并且进一步耦合的控制电路的回跳电路 到分离的掺杂阱区域和形成在掺杂阱区域中的部分快速恢复电路。 控制电路包括响应于控制信号而可调整的阻抗，并被配置为调整隔离掺杂阱阻抗，其中相对于参考电压形成至少一部分快速恢复电路。 可以根据调整控制电路的电阻抗的控制信号来设置对回跳电路的调制触发和保持条件。

    Combination ESD protection circuits and methods
    10.
    发明授权
    Combination ESD protection circuits and methods 有权
    组合式ESD保护电路及方法

    公开(公告)号：US09209620B2

    公开(公告)日：2015-12-08

    申请号：US14109080

    申请日：2013-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Xiaofeng Fan ,  Michael D. Chaine

    IPC: H02H9/00 ,  H02H9/04 ,  H01L27/06 ,  H01L27/02 ,  H01L27/08

    CPC classification number: H02H9/044 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/0617 ,  H01L27/0817 ,  H02H9/046

    Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.

    Abstract translation: 公开了用于保护电路免受静电放电事件的电路，集成电路，装置和方法。 在一个示例性方法中，晶闸管被触发以使用由在晶体管的基极共享的半导体掺杂阱中形成的晶体管提供的漏电流从信号节点传导到参考电压节点。 泄漏电流响应于信号节点处的噪声事件（例如，静电放电（ESD）事件），并且增加半导体掺杂阱的电压以使晶闸管的基极和集电极正向偏置。 触发晶闸管将ESD事件导致的电流导通到参考电压节点。

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