公开(公告)号：US20140071781A1

公开(公告)日：2014-03-13

申请号：US14080302

申请日：2013-11-14

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON ,  Bruce MILLAR

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

Abstract: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

Abstract translation: 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

公开(公告)号：US20130329482A1

公开(公告)日：2013-12-12

申请号：US13966891

申请日：2013-08-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Bruce MILLAR

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.