公开(公告)号：US20140019705A1

公开(公告)日：2014-01-16

申请号：US14027858

申请日：2013-09-16

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON ,  Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。

公开(公告)号：US20130329482A1

公开(公告)日：2013-12-12

申请号：US13966891

申请日：2013-08-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Bruce MILLAR

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

公开(公告)号：US20140133243A1

公开(公告)日：2014-05-15

申请号：US14158215

申请日：2014-01-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Graham ALLAN

IPC: G11C16/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract translation: 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从先前存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

公开(公告)号：US20140013041A1

公开(公告)日：2014-01-09

申请号：US13962062

申请日：2013-08-08

Applicant: Mosaid Technologies Incorporated

Inventor： Peter B. GILLINGHAM

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F13/4243

Abstract: A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.

Abstract translation: 用于布置存储器件的控制器可以发出写入命令而不等待先前发出的读取命令的接收。 寻址的存储器件可以根据读取命令将数据读出到数据总线上，同时根据读取命令之后接收的写入命令写入数据。

公开(公告)号：US20130318287A1

公开(公告)日：2013-11-28

申请号：US13955809

申请日：2013-07-31

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hong Beom PYEON ,  Hunsam JUNG ,  Peter B. GILLINGHAM

IPC: G06F1/08 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F1/08 ,  G06F3/0676 ,  G06F12/0246 ,  G06F13/1689 ,  G11C7/04

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。 系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置 复合存储器件。 响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

公开(公告)号：US20130235659A1

公开(公告)日：2013-09-12

申请号：US13871487

申请日：2013-04-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Graham ALLAN

IPC: G11C16/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US20130249592A1

公开(公告)日：2013-09-26

申请号：US13903319

申请日：2013-05-28

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM

IPC: H03K3/012 ,  H03K19/00

CPC classification number: H03K3/012 ,  H01L2924/0002 ,  H03K19/0005 ,  H03K19/00361 ,  H04L25/0278 ,  H01L2924/00

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract translation: 在具有连接到内部部分的端子的半导体器件中，用于为器件的端子提供管芯端接的终端电路。 终端电路包括多个晶体管，其包括连接在端子和电源之间的至少一个NMOS晶体管和至少一个PMOS晶体管; 以及控制电路，用于以相应的NMOS栅极电压驱动每个NMOS晶体管的栅极并且用相应的PMOS栅极电压驱动每个PMOS晶体管的栅极，所述控制电路被配置为控制NMOS和PMOS栅极电压，以便 当使能片上端接时，将晶体管置于欧姆区域。 电源提供小于每个所述NMOS栅极电压并大于每个所述PMOS栅极电压的电压。