公开(公告)号：US20230268447A1

公开(公告)日：2023-08-24

申请号：US18305537

申请日：2023-04-24

Applicant: Mosaid Technologies Incorporated

Inventor： Hyoung Seub RHIE

IPC: H01L29/792 ,  H01L29/66 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L29/7926 ,  G11C11/5621 ,  G11C16/0483 ,  H01L29/66833 ,  H10B43/27 ,  H10B43/40 ,  G11C2213/71

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

公开(公告)号：US20140112074A1

公开(公告)日：2014-04-24

申请号：US13830135

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C16/14

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract translation: 一种使用现有行解码电路的非易失性存储器件，用于选择性地向至少一个所选择的存储块提供全局擦除电压，以便于擦除所述至少一个所选存储块的所有非易失性存储单元。 更具体地，擦除电压耦合到至少一个所选存储块的存储器单元的单元体或衬底，其中单元体与至少一个其它存储块中的非易失性存储单元的单元体电隔离 。 通过将擦除电压路径与用于驱动所选存储器块的行信号的现有行解码电路进行积分，不需要额外的解码逻辑或电路来将擦除电压提供给至少一个所选择的存储块。

公开(公告)号：US20140104948A1

公开(公告)日：2014-04-17

申请号：US13836028

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

Abstract translation: 具有组织成多个存储器块的存储器阵列的非易失性存储器件，具有平面存储单元或单元堆叠。 存储器件的行解码电路被配置为响应于第一行地址来选择多个存储器块的组，并且响应于第二行地址选择用于接收行信号的组的存储器块。 与每组存储器块相关联的行解码电路可以具有大于单个存储器块的行间距间隔的行间距间隔，并且小于或等于对应于该组存储器块的总行间距间隔。

公开(公告)号：US20140192596A1

公开(公告)日：2014-07-10

申请号：US13830054

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/02

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

Abstract translation: 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。