公开(公告)号：US12218665B2

公开(公告)日：2025-02-04

申请号：US18181983

申请日：2023-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00 ,  H03K19/0185

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

公开(公告)号：US20240305298A1

公开(公告)日：2024-09-12

申请号：US18181983

申请日：2023-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: H03K19/0185 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00

CPC classification number: H03K19/018521 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/10 ,  H03K3/037 ,  H03K19/0005

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

公开(公告)号：US20250119142A1

公开(公告)日：2025-04-10

申请号：US18988186

申请日：2024-12-19

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: H03K19/0185 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.