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公开(公告)号：US20200185010A1
公开(公告)日：2020-06-11
申请号：US16534992
申请日：2019-08-07
发明人： Su-Chueh Lo , Ken-Hui Chen , Kuen-Long Chang , Ming-Chih Hsieh
摘要： A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.
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公开(公告)号：US20170212696A1
公开(公告)日：2017-07-27
申请号：US15006316
申请日：2016-01-26
发明人： Shang-Chi Yang , Su-Chueh Lo
CPC分类号： G06F13/4291 , G06F12/0638 , G06F13/1673 , G06F13/28 , G06F13/4022
摘要： A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.
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公开(公告)号：US20160072486A1
公开(公告)日：2016-03-10
申请号：US14479104
申请日：2014-09-05
发明人： Shang-Chi Yang , Su-Chueh Lo
IPC分类号： H03K5/02 , H01L21/8234 , H01L27/06
CPC分类号： H03K5/023 , G11C7/062 , G11C7/12 , G11C2207/002 , H01L21/8234 , H01L27/0617
摘要： One aspect of the technology is an integrated circuit, comprising a bias circuit and a sense amplifier. The bias circuit has a diode-connected transistor and a first bias voltage. The first bias voltage is represented by a first term inversely dependent on a first mobility of charge carriers of the diode-connected transistor and inversely dependent on a first gate-to-channel dielectric capacitance of the diode-connected transistor. The sense amplifier is coupled to another transistor that has a gate coupled to the first bias voltage of the bias circuit.
摘要翻译： 该技术的一个方面是集成电路，包括偏置电路和读出放大器。 偏置电路具有二极管连接的晶体管和第一偏置电压。 第一偏置电压由与二极管连接的晶体管的电荷载流子的第一迁移率成反比的第一项表示，并且取决于二极管连接晶体管的第一栅极 - 沟道介电电容。 读出放大器耦合到具有与偏置电路的第一偏置电压耦合的栅极的另一个晶体管。
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公开(公告)号：US09275695B2
公开(公告)日：2016-03-01
申请号：US14506768
申请日：2014-10-06
发明人： Chin-Hung Chang , Chia-Jung Chen , Su-Chueh Lo , Ken-Hui Chen , Kuen-Long Chang
CPC分类号： G11C7/1048 , G11C7/06 , G11C7/08 , G11C7/106 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.
摘要翻译： 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前半页数据。 所选择的字线，第一和第二全局位线组保持预充电。
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5.发明授权Method and apparatus for leakage suppression in flash memory in response to external commands 有权响应于外部命令，闪存中泄漏抑制的方法和装置公开(公告)号：US09093172B2
公开(公告)日：2015-07-28
申请号：US14249270
申请日：2014-04-09
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。
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公开(公告)号：US20240305298A1
公开(公告)日：2024-09-12
申请号：US18181983
申请日：2023-03-10
发明人： Yi-Fan Chang , Su-Chueh Lo , Jeng-Kuan Lin
IPC分类号： H03K19/0185 , G06F3/06 , G11C7/10 , H03K3/037 , H03K19/00
CPC分类号： H03K19/018521 , G06F3/0604 , G06F3/0656 , G06F3/0679 , G11C7/10 , H03K3/037 , H03K19/0005
摘要： Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.
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公开(公告)号：US11301151B2
公开(公告)日：2022-04-12
申请号：US16870848
申请日：2020-05-08
发明人： Chun-Hsiung Hung , Su-Chueh Lo
IPC分类号： G06F3/06 , H01L25/065
摘要： A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.
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公开(公告)号：US10657051B2
公开(公告)日：2020-05-19
申请号：US15841640
申请日：2017-12-14
发明人： Su-Chueh Lo , Chun-Yu Liao
IPC分类号： G11C16/26 , G06F12/06 , G11C11/417 , G11C11/16 , G11C7/20 , G11C7/10 , G11C11/413 , G11C29/50 , G06F3/06
摘要： Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.
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公开(公告)号：US10289596B2
公开(公告)日：2019-05-14
申请号：US15411731
申请日：2017-01-20
发明人： Ken-Hui Chen , Kuen-Long Chang , Su-Chueh Lo , Chun-Yu Liao
摘要： A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.
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公开(公告)号：US09450577B1
公开(公告)日：2016-09-20
申请号：US14742160
申请日：2015-06-17
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Su-Chueh Lo , Tzu-Ting Chiu
CPC分类号： H03K19/018507
摘要： An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.
摘要翻译： 输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。
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