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公开(公告)号：US11049557B2
公开(公告)日：2021-06-29
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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2.发明申请公开(公告)号：US20190066778A1
公开(公告)日：2019-02-28
申请号：US15687687
申请日：2017-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Yun-Chen Chou , Hsin-Yi Ho
IPC: G11C13/00
Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.
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Patent Agency Ranking
3.发明授权公开(公告)号：US11842769B2
公开(公告)日：2023-12-12
申请号：US17721207
申请日：2022-04-14
Applicant: MACRONIX International Co., Ltd.
Inventor： Tien-Yen Wang , Yun-Chen Chou , Chun-Hsiung Hung
IPC: G11C11/419
CPC classification number: G11C11/419
Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.
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公开(公告)号：US10297316B2
公开(公告)日：2019-05-21
申请号：US15687687
申请日：2017-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Yun-Chen Chou , Hsin-Yi Ho
IPC: G11C13/00
Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.
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公开(公告)号：US12002536B2
公开(公告)日：2024-06-04
申请号：US17705469
申请日：2022-03-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yun-Chen Chou , Tien-Yen Wang , Chun-Hsiung Hung
Abstract: A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.
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6.发明公开公开(公告)号：US20230335187A1
公开(公告)日：2023-10-19
申请号：US17721207
申请日：2022-04-14
Applicant: MACRONIX International Co., Ltd.
Inventor： Tien-Yen Wang , Yun-Chen Chou , Chun-Hsiung Hung
IPC: G11C11/419
CPC classification number: G11C11/419
Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.
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公开(公告)号：US20210020235A1
公开(公告)日：2021-01-21
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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