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公开(公告)号：US10915248B1
公开(公告)日：2021-02-09
申请号：US16533870
申请日：2019-08-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hsiang-Lan Lung , Hsin-Yi Ho
Abstract: An embodiment of the present invention discloses a memory device. The memory device includes a memory controller, a calculation memory and a functional circuit. The calculation memory is coupled to the memory controller, and is configured to receive a plurality of first signals to output a plurality of second signals. Each of the second signals has a reference value. The functional circuit is coupled to the calculation memory, and is configured to indicate the second signal which has the greatest or the smallest reference value among the second signals.
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公开(公告)号：US10297316B2
公开(公告)日：2019-05-21
申请号：US15687687
申请日：2017-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Yun-Chen Chou , Hsin-Yi Ho
IPC: G11C13/00
Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.
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公开(公告)号：US09471485B2
公开(公告)日：2016-10-18
申请号：US13926633
申请日：2013-06-25
Applicant: Macronix International Co., Ltd.
Inventor： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Han-Sung Chen
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201 , G06F2212/7208
Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.
Abstract translation: 一种用于维护数据集的方法包括将数据集的基本副本存储在具有第一写入速度的第一非易失性存储器中，将具有第一非易失性存储器的第一变化数据集中的数据集的改变存储在具有第 第二写入速度，并通过读取基本副本和更改来生成数据集的当前副本。 如果达到第一改变数据集中的阈值数目，则将第一变化数据集的部分或全部移动到第一非易失性存储器中的第二变化数据集中，其中生成步骤包括读取第二变化 数据集。 如果达到第二改变数据集中的阈值数目，则通过读取基本副本和第一和第二非易失性存储器中的改变来生成当前副本。
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公开(公告)号：US20140281175A1
公开(公告)日：2014-09-18
申请号：US14265400
申请日：2014-04-30
Applicant: Macronix International Co., Ltd.
Inventor： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。
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公开(公告)号：US20220344404A1
公开(公告)日：2022-10-27
申请号：US17239306
申请日：2021-04-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho , Hsiang-Lan Lung
Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190066778A1
公开(公告)日：2019-02-28
申请号：US15687687
申请日：2017-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Yun-Chen Chou , Hsin-Yi Ho
IPC: G11C13/00
Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.
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公开(公告)号：US20140281150A1
公开(公告)日：2014-09-18
申请号：US13926633
申请日：2013-06-25
Applicant: Macronix International Co., Ltd.
Inventor： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Han-Sung Chen
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201 , G06F2212/7208
Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.
Abstract translation: 一种用于维护数据集的方法包括将数据集的基本副本存储在具有第一写入速度的第一非易失性存储器中，将具有第一非易失性存储器的第一变化数据集中的数据集的改变存储在具有第 第二写入速度，并通过读取基本副本和更改来生成数据集的当前副本。 如果达到第一改变数据集中的阈值数目，则将第一变化数据集的部分或全部移动到第一非易失性存储器中的第二变化数据集中，其中生成步骤包括读取第二变化 数据集。 如果达到第二改变数据集中的阈值数目，则通过读取基本副本和第一和第二非易失性存储器中的改变来生成当前副本。
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公开(公告)号：US11996148B2
公开(公告)日：2024-05-28
申请号：US17710654
申请日：2022-03-31
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho
IPC: G11C13/00
CPC classification number: G11C13/0059 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/003
Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.
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公开(公告)号：US20230317156A1
公开(公告)日：2023-10-05
申请号：US17710654
申请日：2022-03-31
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho
IPC: G11C13/00
CPC classification number: G11C13/0059 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/003
Abstract: A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.
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公开(公告)号：US11495639B1
公开(公告)日：2022-11-08
申请号：US17239306
申请日：2021-04-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho , Hsiang-Lan Lung
Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.
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