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公开(公告)号：US20210020235A1
公开(公告)日：2021-01-21
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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2.发明授权公开(公告)号：US11710519B2
公开(公告)日：2023-07-25
申请号：US17368705
申请日：2021-07-06
Applicant: Macronix International Co., Ltd.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Cheng-Lin Sung , Yung-Feng Lin
IPC: G11C7/12 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/4094 , G11C11/4099 , G11C16/10 , G11C16/28
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C11/4099 , G11C16/102 , G11C16/28
Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.
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公开(公告)号：US11605431B2
公开(公告)日：2023-03-14
申请号：US17325243
申请日：2021-05-20
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Su-Chueh Lo , Teng-Hao Yeh , Hang-Ting Lue
Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.
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4.发明申请公开(公告)号：US20190066778A1
公开(公告)日：2019-02-28
申请号：US15687687
申请日：2017-08-28
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin , Yun-Chen Chou , Hsin-Yi Ho
IPC: G11C13/00
Abstract: A memory device and associated control methods are provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array having memory cells and a controller. The memory cells are located at intersections of the M bit lines and the N word lines. A selected memory cell including a storage element and a selector switch is electrically connected to an m-th bit line and an n-th word line. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration.
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5.发明授权公开(公告)号：US12198752B2
公开(公告)日：2025-01-14
申请号：US18206422
申请日：2023-06-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Cheng-Lin Sung , Yung-Feng Lin
IPC: G11C16/28 , G11C11/4074 , G11C11/408 , G11C11/4091 , G11C11/4094 , G11C11/4099 , G11C16/10
Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.
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Patent Agency Ranking
公开(公告)号：US11049557B2
公开(公告)日：2021-06-29
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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公开(公告)号：US08659327B2
公开(公告)日：2014-02-25
申请号：US13746374
申请日：2013-01-22
Applicant: Macronix International Co., Ltd.
Inventor： Yung-Feng Lin
IPC: H03K3/00
CPC classification number: H03K17/10 , H03K19/018528
Abstract: An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.
Abstract translation: 输出缓冲器包括第一输出晶体管，第一开关，第二开关和第三开关。 第一输出晶体管连接到用于输出第一工作电压的第一工作电压作为数据信号。 第一开关连接到第一输出晶体管的大部分，用于接收使能信号。 第二开关连接到第一开关和用于接收使能信号的第二工作电压，其中第二工作电压低于第一工作电压。 第三开关包括连接到第一输出晶体管的主体的第一端子，连接到第一开关的控制端子和连接到第一工作电压的第二端子。
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公开(公告)号：US20130135028A1
公开(公告)日：2013-05-30
申请号：US13746374
申请日：2013-01-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Feng Lin
IPC: H03K17/10
CPC classification number: H03K17/10 , H03K19/018528
Abstract: An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.
Abstract translation: 输出缓冲器包括第一输出晶体管，第一开关，第二开关和第三开关。 第一输出晶体管连接到用于输出第一工作电压的第一工作电压作为数据信号。 第一开关连接到第一输出晶体管的大部分，用于接收使能信号。 第二开关连接到第一开关和用于接收使能信号的第二工作电压，其中第二工作电压低于第一工作电压。 第三开关包括连接到第一输出晶体管的主体的第一端子，连接到第一开关的控制端子和连接到第一工作电压的第二端子。
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公开(公告)号：US11631441B2
公开(公告)日：2023-04-18
申请号：US17701044
申请日：2022-03-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuen-Long Chang , Su-Chueh Lo , Yung-Feng Lin
Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.
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公开(公告)号：US20230085583A1
公开(公告)日：2023-03-16
申请号：US17477229
申请日：2021-09-16
Applicant: MACRONIX International Co., Ltd.
Inventor： Yung-Feng Lin , Su-Chueh Lo , Teng-Hao Yeh , Hang-Ting Lue
IPC: G11C16/24 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/11556 , H01L27/11526 , H01L27/11582 , H01L27/11573
Abstract: A three dimension memory device, such as a three dimensional AND flash memory is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches, and a plurality of source line switches. The memory array has a plurality of memory cell rows respectively coupled to a plurality of source lines and bit lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and second transistors. The first transistors are coupled to a common bit line and the bit line. The second transistors are coupled to a common source line and the source lines. The first transistors are P-type transistors or an N-type transistors with a triple-well substrate, and the second transistors are P-type transistor or an N-type transistors with a triple-well substrate.
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