公开(公告)号：US20110221000A1

公开(公告)日：2011-09-15

申请号：US12882038

申请日：2010-09-14

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1045 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.

摘要翻译： 一种制造半导体器件的方法包括在第一晶体管区域中的半导体衬底上形成第一栅电极; 形成通道剂量区域; 以及形成第一源极延伸区域，其中通过使用第一掩模作为掩模并且通过离子注入第一导电类型的第一掺杂剂形成沟道剂量区域，并且覆盖第一栅电极的漏极侧的第一掩模 并且覆盖漏极区域，并且通过使用第二掩模和栅极电极作为掩模并且通过离子注入作为与第一导电类型相反的导电类型的第二导电类型的第二掺杂剂形成第一源极延伸区域， 所述第二掩模覆盖所述第一栅电极的漏极侧并覆盖所述漏极区。

公开(公告)号：US20120038001A1

公开(公告)日：2012-02-16

申请号：US13281503

申请日：2011-10-26

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜形成在硅衬底上的栅电极，形成在硅衬底内的栅电极下方的沟道区，以及形成在p型沟道MOS晶体管上的p型源极区和p型漏极区 硅衬底内的沟道区的相对侧。 在p沟道MOS晶体管中，第一和第二侧壁绝缘膜布置在栅电极的相对的侧壁面上。 第一和第二p型外延区分别形成在硅衬底上的第一和第二侧壁绝缘膜的外侧，并且第一和第二p型外延区被布置成高于栅电极。 存储拉伸应力并经由第一和第二侧壁绝缘膜覆盖栅电极的应力膜连续地布置在第一和第二p型外延区上。

公开(公告)号：US20110233687A1

公开(公告)日：2011-09-29

申请号：US13044875

申请日：2011-03-10

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L29/78 ,  H01L21/336 ,  G03F1/00

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892

摘要： A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask.

摘要翻译： 一种半导体器件制造方法，包括在半导体衬底的内部形成具有第一导电型内部的沟道掺杂层，所述沟道掺杂层形成在除了用于形成低浓度漏极区域的掺杂杂质的漏极杂质区域以外的区域中 并且沟道掺杂层与漏杂质区分离; 通过栅极绝缘膜在所述半导体衬底上形成栅电极; 以及在所述栅电极的第一侧上形成所述半导体衬底内部的低浓度源区，并且在所述栅电极的第二侧上在所述半导体衬底的漏极杂质区域中形成低浓度漏区， 第二导电掺杂剂杂质在半导体衬底的内部，栅电极作为掩模。

公开(公告)号：US20120208336A1

公开(公告)日：2012-08-16

申请号：US13451535

申请日：2012-04-19

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1045 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.

摘要翻译： 一种制造半导体器件的方法包括在第一晶体管区域中的半导体衬底上形成第一栅电极; 形成通道剂量区域; 以及形成第一源极延伸区域，其中通过使用第一掩模作为掩模并且通过离子注入第一导电类型的第一掺杂剂形成沟道剂量区域，并且覆盖第一栅电极的漏极侧的第一掩模 并且覆盖漏极区域，并且通过使用第二掩模和栅极电极作为掩模并且通过离子注入作为与第一导电类型相反的导电类型的第二导电类型的第二掺杂剂形成第一源极延伸区域， 所述第二掩模覆盖所述第一栅电极的漏极侧并覆盖所述漏极区。

公开(公告)号：US20090014804A1

公开(公告)日：2009-01-15

申请号：US12238799

申请日：2008-09-26

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28052 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/7843 ,  H01L29/7845

摘要： To solve the problem, a MISFET covered with an insulating film which generates stress is provided. The MISFET including a gate insulating film; a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion; and a source/drain disposed adjacent to the gate electrode, in which the ratio between the polysilicon portion and the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress through the gate electrode in a channel region of the MISFET.

摘要翻译： 为了解决这个问题，提供了覆盖有产生应力的绝缘膜的MISFET。 MISFET包括栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极，所述栅电极包括多晶硅部分和硅化物部分; 以及与栅电极相邻设置的源极/漏极，其中根据用于增强MISFET的驱动能力的应变确定多晶硅部分和硅化物部分之间的比率，该应变是基于通过 栅极电极在MISFET的沟道区域中。

公开(公告)号：US20080048210A1

公开(公告)日：2008-02-28

申请号：US11853195

申请日：2007-09-11

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L29/161 ,  H01L21/36

CPC分类号： H01L29/1054 ,  A23D9/00 ,  A23D9/06 ,  C11B5/0035 ,  C11B5/0092 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7833

摘要： In a MOS-type semiconductor device in which, on a Si substrate (201), a SiGe layer (202) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer (203), and an insulating layer (204) are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer (203) and the insulting film (204) by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.

摘要翻译： 在Si型基板（201）中，具有比第一半导体层的价带边缘能量值小的价带边缘能量值的SiGe层（202）的MOS型半导体装置， 第一半导体层的迁移率，Si覆盖层（203）和绝缘层（204）依次层叠，将由阈值电压的绝对值向由 或通过Ge的扩散在Si覆盖层（203）和绝缘膜（204）之间的界面附近，通过在Si覆盖层和绝缘膜之间的界面内和附近引起的正电荷中和负的固定电荷来克服 通过NO气体退火向半导体器件表面添加氮原子，从而将阈值电压向更大的值移动。

公开(公告)号：US20090179278A1

公开(公告)日：2009-07-16

申请号：US12411016

申请日：2009-03-25

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/7843

摘要： In a p-type MOS transistor, a gate electrode is partially removed by a predetermined wet etching, so that an upper portion of the gate electrode is formed to be lower than an upper portion of a sidewall insulation film. As a result of such a constitution, in spite of formation of a tensile stress (TSEL) film leading to deterioration of characteristics of a p-type MOS transistor by nature, stresses applied from the TESL film to the gate electrode and the sidewall insulation film are dispersed as indicated by broken arrows in the drawing, and consequently, a compressive stress is applied to a channel region, so that a compressive strain is introduced. As stated above, in the p-type MOS transistor, in spite of formation of the TESL film, in reality, a strain to improve characteristics of the p-type MOS transistor is given to the channel region.

摘要翻译： 在p型MOS晶体管中，通过预定的湿蚀刻部分去除栅电极，使得栅电极的上部形成为低于侧壁绝缘膜的上部。 作为这种结构的结果，尽管形成导致p型MOS晶体管特性劣化的拉伸应力（TSEL）膜，但是从TESL膜施加到栅电极和侧壁绝缘膜的应力 如图中虚线箭头所示分散，因此，对通道区域施加压缩应力，从而引入压缩应变。 如上所述，在p型MOS晶体管中，尽管形成了TESL膜，但实际上，向沟道区域施加了提高p型MOS晶体管的特性的应变。

公开(公告)号：US20080277732A1

公开(公告)日：2008-11-13

申请号：US12176616

申请日：2008-07-21

申请人： Masashi SHIMA

发明人： Masashi SHIMA

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜形成在硅衬底上的栅电极，形成在硅衬底内的栅电极下方的沟道区，以及形成在p型沟道MOS晶体管上的p型源极区和p型漏极区 硅衬底内的沟道区的相对侧。 在p沟道MOS晶体管中，第一和第二侧壁绝缘膜布置在栅电极的相对的侧壁面上。 第一和第二p型外延区分别形成在硅衬底上的第一和第二侧壁绝缘膜的外侧，并且第一和第二p型外延区被布置成高于栅电极。 存储拉伸应力并经由第一和第二侧壁绝缘膜覆盖栅电极的应力膜连续地布置在第一和第二p型外延区上。