公开(公告)号：US5991868A

公开(公告)日：1999-11-23

申请号：US246179

申请日：1994-05-19

申请人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

发明人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

IPC分类号： G06F7/00 ,  G06F9/302 ,  G06F9/32 ,  G06F9/30

CPC分类号： G06F9/30014 ,  G06F9/30058 ,  G06F9/30094

摘要： In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

摘要翻译： 在数据处理装置中，解码单元解码指令。 计算器根据解码结果来操作N位数据。 标志存储单元基于所操作的结果存储对应于具有不同宽度的数据而改变的多个标志组。 选择器根据条件分支指令的方向选择预定的标志组。 分支判断单元通过参照所选择的标志组判断是否采用分支。

公开(公告)号：US20080320454A1

公开(公告)日：2008-12-25

申请号：US11607889

申请日：2006-12-04

申请人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

发明人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

IPC分类号： G06F9/355 ,  G06F9/30 ,  G06F9/45 ,  G06F9/34

CPC分类号： G06F9/30167 ,  G06F8/423 ,  G06F8/447 ,  G06F8/47 ,  G06F8/52 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/34 ,  G06F9/342

摘要： The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

摘要翻译： 本发明公开了一种程序转换单元，用于在处理M位数据（N大于M）的管理N位地址的处理器的源程序中产生机器语言指令，以及运行转换程序的处理器 。 所述程序转换单元包括：用于保持用户指定的数据宽度和指针宽度的参数保持单元; 数据宽度表示在源程序中使用的数据的位数，而指针宽度表示地址的位数; 以及生成单元，用于当由指令操作的变量表示数据时生成用于管理数据宽度的指令，并且当由指令操作的变量表示地址时，生成用于管理指针宽度的指令。

公开(公告)号：USRE40498E1

公开(公告)日：2008-09-09

申请号：US10991367

申请日：2004-11-19

申请人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

发明人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

IPC分类号： G06F9/45

CPC分类号： G06F9/30167 ,  G06F8/423 ,  G06F8/447 ,  G06F8/47 ,  G06F8/52 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/34 ,  G06F9/342

摘要： The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

公开(公告)号：USRE41959E1

公开(公告)日：2010-11-23

申请号：US09662484

申请日：2000-09-14

申请人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

发明人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

IPC分类号： G06F9/45

CPC分类号： G06F9/30167 ,  G06F8/423 ,  G06F8/447 ,  G06F8/47 ,  G06F8/52 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/34 ,  G06F9/342

摘要： The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

摘要翻译： 本发明公开了一种程序转换单元，用于在处理M位数据（N大于M）的管理N位地址的处理器的源程序中产生机器语言指令，以及运行转换程序的处理器 。 所述程序转换单元包括：用于保持用户指定的数据宽度和指针宽度的参数保持单元; 数据宽度表示在源程序中使用的数据的位数，而指针宽度表示地址的位数; 以及生成单元，用于当由指令操作的变量表示数据时生成用于管理数据宽度的指令，并且当由指令操作的变量表示地址时，生成用于管理指针宽度的指令。

公开(公告)号：US5809306A

公开(公告)日：1998-09-15

申请号：US587338

申请日：1996-01-16

申请人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

发明人： Masato Suzuki ,  Hiroshi Kamiyama ,  Shinya Miyaji

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/34 ,  G06F9/355 ,  G06F9/45

CPC分类号： G06F9/30167 ,  G06F8/423 ,  G06F8/447 ,  G06F8/47 ,  G06F8/52 ,  G06F9/30014 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/34 ,  G06F9/342

摘要： The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

摘要翻译： 本发明公开了一种程序转换单元，用于在处理M位数据（N大于M）的管理N位地址的处理器的源程序中产生机器语言指令，以及运行转换程序的处理器 。 所述程序转换单元包括：用于保持用户指定的数据宽度和指针宽度的参数保持单元; 数据宽度表示在源程序中使用的数据的位数，而指针宽度表示地址的位数; 以及生成单元，用于当由指令操作的变量表示数据时生成用于管理数据宽度的指令，并且当由指令操作的变量表示地址时，生成用于管理指针宽度的指令。

公开(公告)号：US5694605A

公开(公告)日：1997-12-02

申请号：US249460

申请日：1994-05-26

申请人： Shinya Miyaji ,  Masato Suzuki ,  Hiroshi Kamiyama

发明人： Shinya Miyaji ,  Masato Suzuki ,  Hiroshi Kamiyama

IPC分类号： G06F9/305 ,  G06F9/45 ,  G06F7/38

CPC分类号： G06F8/447

摘要： A program translator has the following units: An option direction unit for directing a code generation unit to generate or not to generate an amendment instruction to compensate an overflow in an arithmetic operation. A code generation unit for generating an amendment instruction to compensate an overflow by discriminating the type of a data variable to be an operand for an arithmetic operation of a machine instruction when effective width of the data variable designated by an operand is smaller than the width of a register to store the data variable and when an overflow may be caused.

摘要翻译： 程序转换器具有以下单元：用于指示代码生成单元生成或不生成修正指令以补偿算术运算中的溢出的选项指导单元。 一种代码生成单元，用于当由操作数指定的数据变量的有效宽度小于一个操作数的宽度时，通过将数据变量的类型识别为机器指令的算术运算的操作数来生成补偿溢出的修正指令 用于存储数据变量的寄存器以及何时可能引起溢出。

公开(公告)号：US06205534B1

公开(公告)日：2001-03-20

申请号：US09401479

申请日：1999-09-22

申请人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

发明人： Hiroshi Kamiyama ,  Masato Suzuki ,  Shinya Miyaji

IPC分类号： G06F930

CPC分类号： G06F9/30014 ,  G06F9/30058 ,  G06F9/30094

摘要： In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

摘要翻译： 在数据处理装置中，解码单元解码指令。 计算器根据解码结果来操作N位数据。 标志存储单元基于所操作的结果存储对应于具有不同宽度的数据而改变的多个标志组。 选择器根据条件分支指令的方向选择预定的标志组。 分支判断单元通过参照所选择的标志组判断是否采用分支。

公开(公告)号：US20050091478A1

公开(公告)日：2005-04-28

申请号：US10617506

申请日：2003-07-11

申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/00

CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

摘要翻译： 解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥， 第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

公开(公告)号：US5847978A

公开(公告)日：1998-12-08

申请号：US721681

申请日：1996-09-27

申请人： Satoshi Ogura ,  Shinya Miyaji ,  Nobuo Higaki ,  Masato Suzuki

发明人： Satoshi Ogura ,  Shinya Miyaji ,  Nobuo Higaki ,  Masato Suzuki

IPC分类号： G06F7/38 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305

CPC分类号： G06F7/57 ,  G06F9/3001 ,  G06F2207/382 ,  G06F7/49921

摘要： A processor including an arithmetic operation circuit and a saturation operation correction circuit both of which are connected in parallel to a register and a data bus and are activated by respective operation instructions. The saturation operation correction circuit judges whether an output from a register file exceeds either of a predetermined upper-most value and a predetermined lower-most value, and selectively outputs one of an operation result, the upper-most value, and the lower-most value.

摘要翻译： 一种处理器，包括算术运算电路和饱和运算校正电路，二者并联连接到寄存器和数据总线，并由相应的操作指令激活。 饱和运算校正电路判断来自寄存器堆的输出是否超过预定的最高值和预定的最低值，并且选择性地输出运算结果，最高值和最低者 值。

公开(公告)号：US06606703B2

公开(公告)日：2003-08-12

申请号：US09756068

申请日：2001-01-08

申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

IPC分类号： G06F1500

CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

摘要： Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

摘要翻译： 处理器和指令转换装置，包括当使用条件指令时减少指令类型数量和处理器硬件比例的技术。 处理器包括凝视保持单元，获取单元，解码单元，判断单元和执行单元。 当由解码单元解码时，判断单元判断状态保持单元更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态。 当判断为肯定时，执行单元执行由解码单元解码的第一条件指令中由操作码指定的操作。 指令集被分配具有第一状态条件的第一条件指令，该第一状态条件与用于未分配的第二条件指令的第二状态条件相互排斥，所述第二状态条件具有相同的操作代码。