公开(公告)号：US09947659B2

公开(公告)日：2018-04-17

申请号：US15122379

申请日：2015-05-25

Applicant: MediaTek Inc.

Inventor： Chang-Tzu Wang ,  Bo-Shih Huang

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/0886 ,  H01L23/535 ,  H01L27/027 ,  H01L29/785

Abstract: The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of the finFET units includes a substrate having a fin along a first direction. A first metal strip pattern and a second metal strip pattern are formed on the fin, extending along a second direction that is different from the first direction. The first and second metal strip patterns are conformally formed on opposite sidewalls and a top surface of the fin, respectively. A first contact and a second contact are formed on the fin. The first and second metal strip patterns are disposed between the first and second contacts. A first dummy contact is formed on the fin, sandwiched between the first and second metal strip patterns.

公开(公告)号：US10236285B2

公开(公告)日：2019-03-19

申请号：US15495185

申请日：2017-04-24

Applicant: MediaTek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

公开(公告)号：US09437590B2

公开(公告)日：2016-09-06

申请号：US14608752

申请日：2015-01-29

Applicant: MediaTek Inc.

Inventor： Chang-Tzu Wang

IPC: H02H9/00 ,  H01L29/66 ,  H01L27/02 ,  H01L29/10 ,  H01L29/04 ,  H01L29/16 ,  H01L23/60

CPC classification number: H01L27/0262 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0266 ,  H01L29/04 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/7436

Abstract: An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.

Abstract translation: 提供了设置在基板上的ESD装置。 ESD器件包括第一阱，第二阱，第一多晶硅区，第二多晶硅区和第一保护层。 第一阱具有第一导电类型并且设置在基板上。 第二阱具有第二导电类型，设置在衬底上并与第一阱相邻。 第一多晶硅区域设置在第一阱上。 第二多晶硅区域设置在第二阱上。 第一保护层覆盖第一阱，第二阱，第一多晶硅区域和第二多晶硅区域的部分。 在第一阱和第二阱的部分中没有掺杂区域被第一保护层覆盖，并且在第一多晶硅区域和第二多晶硅区域之间。

公开(公告)号：US09666576B2

公开(公告)日：2017-05-30

申请号：US14884981

申请日：2015-10-16

Applicant: MediaTek Inc.

Inventor： Chien-Kai Huang ,  Yuan-Fu Chung ,  Bo-Shih Huang ,  Chang-Tzu Wang

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

公开(公告)号：US20170221879A1

公开(公告)日：2017-08-03

申请号：US15353702

申请日：2016-11-16

Applicant: MEDIATEK INC.

Inventor： Chang-Tzu Wang ,  Tzu-Yi Yang

IPC: H01L27/02

CPC classification number: H01L27/0285 ,  H01L27/0288 ,  H01L29/785 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit has an ESD detection circuit, an ESD clamp circuit, and a leakage current reduction circuit. The ESD detection circuit generates an ESD trigger signal when an ESD event is detected in a normal mode. The ESD clamp circuit has a first transistor and a second transistor. The first transistor has a first connection terminal coupled to a first power rail, a control terminal, and a second connection terminal. A bias voltage is supplied to the control terminal of the first transistor in the normal mode. The second transistor has a first connection terminal coupled to the second connection terminal of the first transistor, a control terminal, and a second connection terminal coupled to a second power rail. The ESD trigger signal is transmitted to the control terminal of the second transistor. The leakage current reduction circuit provides the bias voltage to the first transistor.