公开(公告)号：US12230622B2

公开(公告)日：2025-02-18

申请号：US17938965

申请日：2022-09-07

Applicant: MEDIATEK INC.

Inventor： Ya-Lun Yang ,  Wen-Chou Wu ,  Che-Hung Kuo

IPC: H05K1/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H05K1/18 ,  H01L23/00

Abstract: An electronic device includes a main printed circuit board (PCB) assembly comprising a bottom PCB and a semiconductor package mounted on an upper surface of the bottom PCB. The semiconductor package includes a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die and the top surface of the substrate are encapsulated by a molding compound. A top PCB is mounted on the semiconductor package through first connecting elements.

公开(公告)号：US20230307421A1

公开(公告)日：2023-09-28

申请号：US18203631

申请日：2023-05-30

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Tai-Yu Chen ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/17 ,  H10B80/00

Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.

公开(公告)号：US11710688B2

公开(公告)日：2023-07-25

申请号：US17363459

申请日：2021-06-30

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105

Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US10468341B2

公开(公告)日：2019-11-05

申请号：US16232129

申请日：2018-12-26

Applicant: MEDIATEK INC.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Che-Hung Kuo ,  Che-Ya Chou ,  Wei-Che Huang

IPC: H01L23/485 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

公开(公告)号：US12021013B2

公开(公告)日：2024-06-25

申请号：US17547127

申请日：2021-12-09

Applicant: MEDIATEK INC.

Inventor： Chiang-Lin Yen ,  Che-Hung Kuo

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49822

Abstract: A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer.

公开(公告)号：US11908767B2

公开(公告)日：2024-02-20

申请号：US17545015

申请日：2021-12-08

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu ,  Chia-Hao Hsu

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822

Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

公开(公告)号：US20230110957A1

公开(公告)日：2023-04-13

申请号：US17938965

申请日：2022-09-07

Applicant: MEDIATEK INC.

Inventor： Ya-Lun Yang ,  Wen-Chou Wu ,  Che-Hung Kuo

IPC: H01L25/18 ,  H05K1/18 ,  H05K1/14 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L23/498

Abstract: An electronic device includes a main printed circuit board (PCB) assembly comprising a bottom PCB and a semiconductor package mounted on an upper surface of the bottom PCB. The semiconductor package includes a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die and the top surface of the substrate are encapsulated by a molding compound. A top PCB is mounted on the semiconductor package through first connecting elements.

公开(公告)号：US20220246508A1

公开(公告)日：2022-08-04

申请号：US17547127

申请日：2021-12-09

Applicant: MEDIATEK INC.

Inventor： Chiang-Lin Yen ,  Che-Hung Kuo

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer.

公开(公告)号：US20210036405A1

公开(公告)日：2021-02-04

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

公开(公告)号：US12230560B2

公开(公告)日：2025-02-18

申请号：US17546191

申请日：2021-12-09

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.