公开(公告)号：US11854784B2

公开(公告)日：2023-12-26

申请号：US17989498

申请日：2022-11-17

申请人： MediaTek Inc.

发明人： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/13024

摘要： A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US11450606B2

公开(公告)日：2022-09-20

申请号：US16430076

申请日：2019-06-03

申请人： MediaTek Inc.

发明人： Yen-Yao Chi ,  Nai-Wei Liu ,  Tzu-Hung Lin ,  Ta-Jen Yu ,  Wen-Sung Hsu

IPC分类号： H01L23/40 ,  H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

摘要： A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US10756040B2

公开(公告)日：2020-08-25

申请号：US15881063

申请日：2018-01-26

申请人： MEDIATEK INC.

发明人： Ta-Jen Yu ,  Chi-Yuan Chen ,  Wen-Sung Hsu

IPC分类号： H01L23/485 ,  H01L23/488 ,  H01L23/525 ,  H01L29/40 ,  H01L23/48 ,  H01L23/498 ,  H01L23/02 ,  H01L23/04 ,  H01L23/12 ,  H01L23/00 ,  H01L23/31

摘要： The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

公开(公告)号：US20200091070A1

公开(公告)日：2020-03-19

申请号：US16430076

申请日：2019-06-03

申请人： MediaTek Inc.

发明人： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

摘要： A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US11791266B2

公开(公告)日：2023-10-17

申请号：US17886704

申请日：2022-08-12

申请人： MediaTek Inc.

发明人： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC分类号： H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5283 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401

摘要： A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US20230307421A1

公开(公告)日：2023-09-28

申请号：US18203631

申请日：2023-05-30

申请人： MEDIATEK INC.

发明人： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Tai-Yu Chen ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/17 ,  H10B80/00

摘要： A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.

公开(公告)号：US20230282604A1

公开(公告)日：2023-09-07

申请号：US18106499

申请日：2023-02-07

申请人： MEDIATEK INC.

发明人： Ta-Jen Yu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Isabella Song ,  Wen-Chin Tsai

IPC分类号： H01L23/00 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/3135 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/14361 ,  H01L2924/1431 ,  H01L2224/13644 ,  H01L2224/13082 ,  H01L2224/13575 ,  H01L2224/13005 ,  H01L2224/1357 ,  H01L2924/1011

摘要： A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.

公开(公告)号：US20230073399A1

公开(公告)日：2023-03-09

申请号：US17989498

申请日：2022-11-17

申请人： MediaTek Inc.

发明人： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

摘要： A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US20180076166A1

公开(公告)日：2018-03-15

申请号：US15638388

申请日：2017-06-30

申请人： MEDIATEK INC.

发明人： Ta-Jen Yu ,  Yu-Sheng Hung ,  Wen-Sung Hsu

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81

摘要： A method for fabricating a semiconductor is disclosed. A carrier substrate is provided. A redistribution layer (RDL) structure is formed on the carrier substrate. The RDL structure comprises at least a bump pad. A semiconductor die is mounted on the RDL structure. A molding compound is formed on the semiconductor die and the RDL structure. The carrier substrate is removed to reveal a plurality of solder ball pads of the RDL structure. A plurality of conductive structures are formed on the solder ball pads.

公开(公告)号：US09633936B2

公开(公告)日：2017-04-25

申请号：US14980445

申请日：2015-12-28

申请人： MediaTek Inc.

发明人： Wen-Sung Hsu ,  Tzu-Hung Lin ,  Ta-Jen Yu

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.