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    Semiconductor package structure
    1.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US11710688B2

    公开(公告)日：2023-07-25

    申请号：US17363459

    申请日：2021-06-30

    Applicant: MEDIATEK INC.

    Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

    IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

    CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105

    Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

    Semiconductor package structure
    5.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US12165961B2

    公开(公告)日：2024-12-10

    申请号：US18329721

    申请日：2023-06-06

    Applicant: MEDIATEK INC.

    Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

    Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

    LATERAL DIODE FOR BACKSIDE POWER RAIL APPLICATION
    7.
    发明申请
    LATERAL DIODE FOR BACKSIDE POWER RAIL APPLICATION 有权

    公开(公告)号：US20240379549A1

    公开(公告)日：2024-11-14

    申请号：US18638650

    申请日：2024-04-17

    Applicant: MEDIATEK INC.

    Inventor： Shih-Chuan Chiu ,  Chia-Hsin Hu ,  Zheng Zeng

    IPC: H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/861

    Abstract: The present invention provides a semiconductor structure, wherein the semiconductor structure includes an oxide definition region, a plurality of metal gate structures and a plurality of S/D contacts. The oxide definition region is disposed over a semiconductor substrate and surrounded by insulating regions. The plurality of metal gate structures are disposed on an N-well or a P-well manufactured on the semiconductor substrate. The plurality of S/D contacts are disposed on the N-well or the P-well manufactured on the semiconductor substrate. In addition, the plurality of metal gate structures, the plurality of S/D contacts and the at least one dummy gate structure are within the oxide definition region.

    Semiconductor device structure
    9.
    发明授权
    Semiconductor device structure 有权

    公开(公告)号：US11367788B2

    公开(公告)日：2022-06-21

    申请号：US16853889

    申请日：2020-04-21

    Applicant: MEDIATEK INC.

    Inventor： Jing-Chyi Liao ,  Ching-Chung Ko ,  Zheng Zeng

    IPC: H01L29/78

    Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.

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