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公开(公告)号：US10444779B2
公开(公告)日：2019-10-15
申请号：US15730877
申请日：2017-10-12
Applicant: MEDIATEK INC.
Inventor： Hao-Yuan Lin , Chia-Hua Chou , Yen-Hsun Hsu
Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.
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公开(公告)号：US20180120874A1
公开(公告)日：2018-05-03
申请号：US15853970
申请日：2017-12-26
Applicant: MEDIATEK INC.
Inventor： Chin-Hsun Chen , Hao-Yuan Lin , Chia-Hua Chou
Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
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公开(公告)号：US10326361B2
公开(公告)日：2019-06-18
申请号：US15907225
申请日：2018-02-27
Applicant: MediaTek Inc.
Inventor： Nien-Hui Kung , Chia-Hua Chou , Yen-Hsun Hsu
Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.
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公开(公告)号：US09886044B2
公开(公告)日：2018-02-06
申请号：US15043687
申请日：2016-02-15
Applicant: MediaTek Inc.
Inventor： Chin-Hsun Chen , Hao-Yuan Lin , Chia-Hua Chou
Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
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公开(公告)号：US20180262105A1
公开(公告)日：2018-09-13
申请号：US15907225
申请日：2018-02-27
Applicant: MediaTek Inc.
Inventor： Nien-Hui Kung , Chia-Hua Chou , Yen-Hsun Hsu
Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.
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Patent Agency Ranking
公开(公告)号：US11848606B2
公开(公告)日：2023-12-19
申请号：US17725561
申请日：2022-04-21
Applicant: MEDIATEK INC.
Inventor： Chia-Hua Chou , Yen-Hsun Hsu
CPC classification number: H02M3/04 , H02M1/007 , H02M3/1584
Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.
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公开(公告)号：US20220376615A1
公开(公告)日：2022-11-24
申请号：US17725561
申请日：2022-04-21
Applicant: MEDIATEK INC.
Inventor： Chia-Hua Chou , Yen-Hsun Hsu
IPC: H02M3/04
Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.
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公开(公告)号：US10539972B2
公开(公告)日：2020-01-21
申请号：US15853970
申请日：2017-12-26
Applicant: MEDIATEK INC.
Inventor： Chin-Hsun Chen , Hao-Yuan Lin , Chia-Hua Chou
Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
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公开(公告)号：US20180120880A1
公开(公告)日：2018-05-03
申请号：US15730877
申请日：2017-10-12
Applicant: MEDIATEK INC.
Inventor： Hao-Yuan Lin , Chia-Hua Chou , Yen-Hsun Hsu
Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.
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公开(公告)号：US20170308153A1
公开(公告)日：2017-10-26
申请号：US15436868
申请日：2017-02-20
Applicant: MEDIATEK INC.
Inventor： Chia-Hua Chou , Yen-Hsun Hsu
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/263 , G06F1/28 , G06F1/305 , G06F1/3203 , G06F1/3296 , H02M3/1584 , H02M2001/008 , Y02D10/172
Abstract: A power delivery system for a multi-core processor chip includes: a plurality of first power delivery units and a plurality of second power delivery units. The plurality of first power delivery units are coupled to a first power supply device. Each of the first power delivery units is arranged to supply power from the first power supply device to a core of the multi-core processor chip. The plurality of second power delivery units are coupled to a second power supply device. Each of the second power delivery units is arranged to selectively supply power from the second power supply to a core of the multi-core processor chip according to a level of a core voltage required by the core of the multi-core processor chip.
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