公开(公告)号：US07248635B1

公开(公告)日：2007-07-24

申请号：US09620373

申请日：2000-07-20

申请人： Michael R. Arneson ,  Terrance L. Bowman ,  Frank N. Cornett ,  John F. DeRyckere ,  Brian T. Hillert ,  Philip N. Jenkins ,  Nan Ma ,  Joseph M. Placek ,  Rodney Ruesch ,  Gregory M. Thorson

发明人： Michael R. Arneson ,  Terrance L. Bowman ,  Frank N. Cornett ,  John F. DeRyckere ,  Brian T. Hillert ,  Philip N. Jenkins ,  Nan Ma ,  Joseph M. Placek ,  Rodney Ruesch ,  Gregory M. Thorson

IPC分类号： H04B3/00 ,  H03H7/38

CPC分类号： H04L25/03878 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

摘要： The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.

摘要翻译： 本发明涉及包括链路级协议，驱动器，接收机和消除器/均衡器的通信信道。 链路级协议提供了无DC信号编码和恢复的逻辑，并支持许多功能，包括CRC错误检测和消息重发，以适应介质上不常见的位错误。 消除器/均衡器为不稳定的数据信号提供均衡，并且还提供同时的双向数据传输。 接收器通过消除数据信号之间的同步错误或倾斜来提供位去偏移。 驱动器通过监视通信介质的特性（如电压或温度）以及在信号驱动器中提供匹配的输出阻抗来提供阻抗控制，以便在数据传播通过通信介质时发生较少的失真。

公开(公告)号：US06803872B2

公开(公告)日：2004-10-12

申请号：US10143413

申请日：2002-05-09

申请人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

发明人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

IPC分类号： H03M136

CPC分类号： H03K5/135 ,  H03K2005/00208

摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

摘要翻译： 对早期到达信号提供附加延迟的电路，使得所有数据信号到达具有相同路径延迟的接收锁存器。 还控制转发的时钟参考的延迟，使得捕获时钟边缘将被最佳地定位在正交附近（取决于锁存器设置/保持要求）。 该电路连续适应数据和时钟路径延迟变化，并且相位测量的数字滤波可以减少抖动数据沿引起的误差。 电路仅利用实现目标所需的最小延迟量，从而限制任何非预期的抖动。 特别地，具有精细延迟调整的可编程差分延迟电路被设计为允许ASICS之间的偏斜最小化。 这包括数据位之间，数据位和时钟之间的偏差以及最小化ASICS之间通道中的总体偏移。

公开(公告)号：US06486723B1

公开(公告)日：2002-11-26

申请号：US10142472

申请日：2002-05-09

申请人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

发明人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

IPC分类号： H03H1126

CPC分类号： H03K5/135 ,  H03K2005/00208

摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

公开(公告)号：US06417713B1

公开(公告)日：2002-07-09

申请号：US09475466

申请日：1999-12-30

申请人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

发明人： John F. DeRyckere ,  Philip Nord Jenkins ,  Frank Nolan Cornett

IPC分类号： H03H1126

CPC分类号： H03K5/135 ,  H03K2005/00208

摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.