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    SYSTEM AND METHOD FOR ADAPTIVELY DESKEWING PARALLEL DATA SIGNALS RELATIVE TO A CLOCK
    1.
    发明申请
    SYSTEM AND METHOD FOR ADAPTIVELY DESKEWING PARALLEL DATA SIGNALS RELATIVE TO A CLOCK 有权
    与时钟相关的适应性平行数据信号的系统和方法

    公开(公告)号：US20090034673A1

    公开(公告)日：2009-02-05

    申请号：US12247122

    申请日：2008-10-07

    申请人： Philip Nord Jenkins ,  Frank N. Cornett

    发明人： Philip Nord Jenkins ,  Frank N. Cornett

    IPC分类号： H04L7/00 ,  H03L7/00

    CPC分类号： G06F1/10 ,  H04L7/0041 ,  H04L7/02

    摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

    摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。

    Determining A High Data Rate For Backchannel Communications For Initialization of High-Speed Networks
    2.
    发明申请
    Determining A High Data Rate For Backchannel Communications For Initialization of High-Speed Networks 有权
    确定用于高速网络初始化的Backchannel通信的高数据速率

    公开(公告)号：US20150092791A1

    公开(公告)日：2015-04-02

    申请号：US14142139

    申请日：2013-12-27

    申请人： FRANK N. CORNETT ,  BRENT R. ROTHERMEL

    发明人： FRANK N. CORNETT ,  BRENT R. ROTHERMEL

    IPC分类号： H04L1/00 ,  H04L7/00

    CPC分类号： H04L1/0002 ,  H04L1/0015 ,  H04L1/0034 ,  H04L7/0087 ,  H04L25/03343 ,  H04L25/03987 ,  H04L25/4906 ,  H04L27/01 ,  H04L27/2608 ,  H04L41/0806 ,  H04N7/17309 ,  Y02D50/10

    摘要： One embodiment provides a network controller. The network controller includes physical interface (PHY) circuitry comprising transmitter circuitry configured to transmit data frames to a link partner in communication with the transmit circuitry over a channel link. The network controller also includes a link speed cycling module configured to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period is sufficient to allow the link partner to lock on to the transmitted data frames.

    摘要翻译： 一个实施例提供一种网络控制器。 网络控制器包括物理接口（PHY）电路，其包括被配置为通过信道链路与发射电路通信的链路伙伴发送数据帧的发射机电路。 网络控制器还包括链路速度循环模块，其被配置为在PHY电路初始化时使得发射机电路使用至少一个高速率链路速度将数据帧发送到链路伙伴。 网络控制器还包括均衡预设模块，其被配置为当发射机电路正在向链路伙伴发送数据帧时向发射机电路施加至少一个均衡预设置。 链路速度模块还被配置为使得发射机电路针对发射机驻留时间段驻留至少一个高速链路速度的至少一个均衡预设置。 发射机停留时间足以允许链路伙伴锁定发送的数据帧。

    System and method for adaptively deskewing parallel data signals relative to a clock
    3.
    发明授权
    System and method for adaptively deskewing parallel data signals relative to a clock 有权
    用于相对于时钟自适应地偏移并行数据信号的系统和方法

    公开(公告)号：US08031823B2

    公开(公告)日：2011-10-04

    申请号：US12247122

    申请日：2008-10-07

    申请人： Philip Nord Jenkins ,  Frank N. Cornett

    发明人： Philip Nord Jenkins ,  Frank N. Cornett

    IPC分类号： H04L7/00

    CPC分类号： G06F1/10 ,  H04L7/0041 ,  H04L7/02

    摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

    摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。

    System and method for adaptively deskewing parallel data signals relative to a clock
    5.
    发明授权
    System and method for adaptively deskewing parallel data signals relative to a clock 有权
    用于相对于时钟自适应地偏移并行数据信号的系统和方法

    公开(公告)号：US07433441B2

    公开(公告)日：2008-10-07

    申请号：US11405387

    申请日：2006-04-17

    申请人： Philip Nord Jenkins ,  Frank N. Cornett

    发明人： Philip Nord Jenkins ,  Frank N. Cornett

    IPC分类号： H04L7/00

    CPC分类号： G06F1/10 ,  H04L7/0041 ,  H04L7/02

    摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

    摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。

    High gain, programmable differential amplifier circuitry
    7.
    发明授权
    High gain, programmable differential amplifier circuitry 失效
    高增益，可编程差分放大器电路

    公开(公告)号：US4825173A

    公开(公告)日：1989-04-25

    申请号：US145933

    申请日：1988-01-18

    申请人： Frank N. Cornett

    发明人： Frank N. Cornett

    IPC分类号： H03G1/00 ,  H03G5/10 ,  H03F3/45

    CPC分类号： H03G5/10 ,  H03G1/0017

    摘要： An amplifier includes a first differential pair of transistors with commonly connected input electrodes also connected to a variable current sink. A common mode voltage control circuit includes a second differential pair of transistors, one of which has a control electrode coupled to the output electrodes of the first differential pair. The second differential pair provides control signals to the variable current sink to regulate the common mode output voltage. Current control circuitry is coupled to the variable current sink to allow adjustment of the gain, bandwith or power dissipation of the first differential pair.

    摘要翻译： 放大器包括具有共同连接的输入电极的第一差分对晶体管，其也连接到可变电流吸收器。 共模电压控制电路包括第二差分对晶体管，其中之一具有耦合到第一差分对的输出电极的控制电极。 第二差分对向可变电流吸收器提供控制信号以调节共模输出电压。 电流控制电路耦合到可变电流吸收器，以允许调整第一差分对的增益，带宽或功率耗散。

    Pipelined A/D converter
    8.
    发明授权
    Pipelined A/D converter 失效
    流水线A / D转换器

    公开(公告)号：US4745394A

    公开(公告)日：1988-05-17

    申请号：US033717

    申请日：1987-04-03

    申请人： Frank N. Cornett

    发明人： Frank N. Cornett

    IPC分类号： H03M1/00 ,  H03M1/44

    CPC分类号： H03M1/1071 ,  H03M1/44

    摘要： An A/D converter which utilizes a plurality of series connected stages is disclosed. Each stage produces a single digital output bit. Errors are dynamically compensated utilizing alignment cycles. Error correction circuitry statistically analyzes an alignment signal during an alignment cycle. Various feedback paths form within each stage during an alignment cycle, and error compensation signals achieve optimum values which compensate for errors within each stage.

    摘要翻译： 公开了一种利用多个串联连接级的A / D转换器。 每个阶段产生单个数字输出位。 使用对齐周期动态补偿错误。 误差校正电路在对齐周期期间统计分析对准信号。 在对齐周期期间，在每个阶段内形成各种反馈路径，并且误差补偿信号实现了补偿每个阶段内的误差的最佳值。

    Frequency shift keyed demodulation system
    9.
    发明授权
    Frequency shift keyed demodulation system 失效
    频移键控解调系统

    公开(公告)号：US4554509A

    公开(公告)日：1985-11-19

    申请号：US644296

    申请日：1984-08-27

    申请人： Frank N. Cornett

    发明人： Frank N. Cornett

    IPC分类号： H04L27/18 ,  H04L27/22 ,  H04L27/233 ,  H04L27/14

    CPC分类号： H04L27/22 ,  H04L27/2338

    摘要： A demodulator for continuous phase frequency shift keyed signals is implemented through the medium of computer software and processes incoming signals which are initially passed through an interference reduction filter. The disclosed demodulation algorithm makes use of the fact that the phase is continuous between adjacent symbols, as well as other symbol to symbol correlations, to reduce the error rate by processing a string of symbols utilizing a two step symbol decision process, instead of merely demodulating a symbol from a time slice of the received signal. The two step symbol decision process consists of a forward and reverse pass, wherein a candidate symbol predecessor is recursively chosen for each symbol, according to a maximum likelihood decision criterion, on the forward pass. Once a singular candidate predecessor is encountered, a reverse pass is initiated, so that a unique sequence of symbols is chosen back to a previously encountered singular predecessor.

    摘要翻译： 用于连续相位频移键控信号的解调器通过计算机软件介质来实现，并处理最初通过干扰抑制滤波器的输入信号。 所公开的解调算法利用相邻符号之间的相位以及其它符号与符号相关性的事实，通过使用两步符号决定处理来处理符号串来减少错误率，而不是仅仅解调 来自接收信号的时间片的符号。 两步符号决定处理包括正向和反向传递，其中根据最大似然判决准则在前向传递中递归地针对每个符号选择候选符号前导。 一旦遇到了一个奇异的候选前辈，就会启动一个反向传递，这样一个唯一的符号序列被选择回到先前遇到的单个前辈。

    Backchannel Communications For Initialization of High-Speed Networks
    10.
    发明申请
    Backchannel Communications For Initialization of High-Speed Networks 有权
    用于初始化高速网络的通道通信

    公开(公告)号：US20150131708A1

    公开(公告)日：2015-05-14

    申请号：US14075346

    申请日：2013-11-08

    申请人： Frank N. Cornett ,  Brent R. Rothermel

    发明人： Frank N. Cornett ,  Brent R. Rothermel

    IPC分类号： H04L25/03

    CPC分类号： H04L41/0806 ,  H04B1/40 ,  H04H20/67 ,  H04L1/0001 ,  H04L1/0041 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03987 ,  H04L27/01 ,  H04L2025/03808 ,  H04N7/17309 ,  H04N19/146 ,  H04N21/6118 ,  H04N21/6168

    摘要： One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.

    摘要翻译： 一个实施例提供一种网络控制器。 网络控制器包括调制模块。 调制模块包括被配置为产生第一高速比特序列的高速率（HR）比特序列发生器，被配置为对第一低比特率比特流进行编码的编码器电路，包括反向信道信息的第一低比特率比特流和配置成 将编码的第一低速比特流调制到第一高比特比特序列上。 网络控制器还包括被配置为在链路初始化时段期间将调制的第一HR比特序列发送到链路伙伴的发送电路。