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7 条记录 (耗时 0.012 秒)

    Bipolar ECL to inverted CMOS level translator
    2.
    发明授权
    Bipolar ECL to inverted CMOS level translator 失效
    双极ECL反相CMOS电平转换器

    公开(公告)号：US5424658A

    公开(公告)日：1995-06-13

    申请号：US165156

    申请日：1993-12-10

    申请人： Mark R. Sikkink ,  Terrance L. Bowman

    发明人： Mark R. Sikkink ,  Terrance L. Bowman

    IPC分类号： H03K19/018 ,  H03K19/0185

    CPC分类号： H03K19/01812

    摘要： A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.

    摘要翻译： 可以实现为双极ECL集成电路的一部分的电平移动电路提供适用于驱动低电压CMOS集成电路的可靠的开关和电平移位输出。 电路包括电平移位电路，其连接以触发高增益正反馈自举电路，以可靠地确保即使在差的信号条件下也能切换。 从一个开关对中取出的输出允许转到VCC，0伏，或被钳位电路钳位到-3.3伏特，代表适合于驱动反向轨道CMOS电路的两个输出状态。

    ECL EPROM with CMOS programming
    4.
    发明授权
    ECL EPROM with CMOS programming 失效
    具有CMOS编程的ECL EPROM

    公开(公告)号：US5075885A

    公开(公告)日：1991-12-24

    申请号：US287980

    申请日：1988-12-21

    申请人： Douglas D. Smith ,  Robert A. Kertis ,  Terrance L. Bowman

    发明人： Douglas D. Smith ,  Robert A. Kertis ,  Terrance L. Bowman

    IPC分类号： G11C17/18 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/10 ,  G11C16/0441 ,  G11C16/26

    摘要： The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element. The MOS memory element is coupled to the programming (writing) path, and the ECL pass element is coupled to the read path with a bipolar output transistor.

    BICMOS positive supply voltage reference
    6.
    发明授权
    BICMOS positive supply voltage reference 失效
    BICMOS正电源电压参考

    公开(公告)号：US5149988A

    公开(公告)日：1992-09-22

    申请号：US610724

    申请日：1990-11-07

    申请人： Douglas D. Smith ,  Terrance L. Bowman

    发明人： Douglas D. Smith ,  Terrance L. Bowman

    IPC分类号： G05F3/20

    CPC分类号： G05F3/20

    摘要： The present invention provides a voltage reference level using a bipolar output transistor to provide a reference voltage on a reference output line. A control circuit is used for varying the current to the base of the output transistor in response to the load on the reference output line. In addition, the control circuit provides the reference level to the output transistor. The MOS control circuit and the bipolar output transistor are fabricated on the same chip using a BICMOS process. The voltage reference provided by the control circuit is derived from a voltage level provided by a resistor coupled between the positive voltage supply and a current source.

    摘要翻译： 本发明提供使用双极性输出晶体管在基准输出线上提供参考电压的电压参考电平。 控制电路用于响应于参考输出线上的负载改变输出晶体管的基极的电流。 此外，控制电路为输出晶体管提供参考电平。 使用BICMOS工艺在同一芯片上制造MOS控制电路和双极性输出晶体管。 由控制电路提供的电压基准是由耦合在正电压源和电流源之间的电阻提供的电压电平导出的。