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公开(公告)号：US20220342582A1
公开(公告)日：2022-10-27
申请号：US17671423
申请日：2022-02-14
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
IPC: G06F3/06
Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.
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公开(公告)号：US11086716B2
公开(公告)日：2021-08-10
申请号：US16790547
申请日：2020-02-13
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.
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公开(公告)号：US11843393B2
公开(公告)日：2023-12-12
申请号：US17952240
申请日：2022-09-24
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
CPC classification number: H03M13/1111 , H03M13/611
Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.
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公开(公告)号：US20210028795A1
公开(公告)日：2021-01-28
申请号：US16790547
申请日：2020-02-13
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.
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Patent Agency Ranking
公开(公告)号：US11663076B2
公开(公告)日：2023-05-30
申请号：US17825352
申请日：2022-05-26
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
CPC classification number: G06F11/1048 , G06F11/1044
Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.
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公开(公告)号：US10972249B1
公开(公告)日：2021-04-06
申请号：US17022480
申请日：2020-09-16
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
Abstract: A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.
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公开(公告)号：US12014068B2
公开(公告)日：2024-06-18
申请号：US17671423
申请日：2022-02-14
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
IPC: G06F3/06
CPC classification number: G06F3/0652 , G06F3/0619 , G06F3/0673
Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.
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公开(公告)号：US20230094363A1
公开(公告)日：2023-03-30
申请号：US17952240
申请日：2022-09-24
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.
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公开(公告)号：US20220382629A1
公开(公告)日：2022-12-01
申请号：US17825352
申请日：2022-05-26
Applicant: Microchip Technology Inc.
Inventor： Peter John Waldemar Graumann
IPC: G06F11/10
Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.
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