公开(公告)号：US20240330190A1

公开(公告)日：2024-10-03

申请号：US18737526

申请日：2024-06-07

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  David Andrew Roberts ,  Patrick Michael Sheridan ,  Lukasz Burzawa

IPC: G06F12/0882 ,  G06F12/06

CPC classification number: G06F12/0882 ,  G06F12/0646

Abstract: Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.

公开(公告)号：US20230051103A1

公开(公告)日：2023-02-16

申请号：US17403366

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Aliasger Tayeb Zaidy

IPC: G06F3/06 ,  G06N3/04

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to predict a schedule for migrating data between memory devices, which can be part of a memory sub-system.

公开(公告)号：US20220147813A1

公开(公告)日：2022-05-12

申请号：US17092044

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello

IPC: G06N3/08 ,  G06F8/41 ,  G06N3/04

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler is configured to generate instructions executable by the Deep Learning Accelerator from a description of a target artificial neural network. The instructions may call routines in a runtime library that has an embedded artificial neural network configured to predict optimized execution options available to implement the routines. The prediction is based at least in part on a pattern of data being processed in the target artificial neural network and/or a pattern of usages of the routines by the instructions.

公开(公告)号：US12118460B2

公开(公告)日：2024-10-15

申请号：US17092033

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

IPC: G06N3/08 ,  G06F8/41 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F8/41 ,  G06N3/04

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

公开(公告)号：US20230100328A1

公开(公告)日：2023-03-30

申请号：US17867371

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  David Andrew Roberts ,  Patrick Michael Sheridan ,  Lukasz Burzawa

IPC: G06F12/0882 ,  G06F12/06

Abstract: Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.

公开(公告)号：US20220147809A1

公开(公告)日：2022-05-12

申请号：US17092023

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

IPC: G06N3/08 ,  G06N3/04

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A compiler can convert a description of an artificial neural network into a compiler output through optimization and/or selection of hardware options of the integrated circuit device. The compiler output can include parameters of the artificial neural network, instructions executable by processing units of the Deep Learning Accelerator to generate an output of the artificial neural network responsive to an input to the artificial neural network, and hardware options to be stored in registers connected to control hardware configurations of the processing units.

公开(公告)号：US20250036950A1

公开(公告)日：2025-01-30

申请号：US18912182

申请日：2024-10-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

IPC: G06N3/08 ,  G06F8/41 ,  G06N3/04

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

公开(公告)号：US11829627B2

公开(公告)日：2023-11-28

申请号：US17403366

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Aliasger Tayeb Zaidy

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06F3/0647 ,  G06F3/0625 ,  G06F3/0685 ,  G06N3/04 ,  G06N3/08

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to predict a schedule for migrating data between memory devices, which can be part of a memory sub-system.

公开(公告)号：US20220147810A1

公开(公告)日：2022-05-12

申请号：US17092033

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

IPC: G06N3/08 ,  G06N3/04 ,  G06F8/41

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

公开(公告)号：US20220147808A1

公开(公告)日：2022-05-12

申请号：US17092013

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Andre Xian Ming Chang ,  Aliasger Tayeb Zaidy ,  Eugenio Culurciello ,  Jaime Cummins ,  Marko Vitez

IPC: G06N3/08 ,  G06N3/063 ,  G06F9/50 ,  G06F17/16 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.