-
公开(公告)号：US20240231685A9
公开(公告)日：2024-07-11
申请号：US18048292
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0631 , G06F3/0673
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
-
公开(公告)号：US11914473B1
公开(公告)日：2024-02-27
申请号：US18048289
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Tal Sharifie , Chandrakanth Rapalli , Yoav Weinberg
CPC classification number: G06F11/1068 , G06F11/0793 , G06F11/1004
Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
-
公开(公告)号：US12072764B2
公开(公告)日：2024-08-27
申请号：US18048283
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F11/10
CPC classification number: G06F11/108 , G06F11/106
Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
-
公开(公告)号：US20240134567A1
公开(公告)日：2024-04-25
申请号：US18048292
申请日：2022-10-19
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0631 , G06F3/0673
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
-
公开(公告)号：US12292795B2
公开(公告)日：2025-05-06
申请号：US18416967
申请日：2024-01-19
Applicant: Micron Technology, Inc.
Inventor： Tal Sharifie , Chandrakanth Rapalli , Yoav Weinberg
Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system receives data units from a host device. A first controller of the memory system generates a protocol unit using the data units. A second controller of the memory system generates a data storage unit using data from the protocol unit, and stores the data unit to a memory device. The memory system performs error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system, for a write operation, re-requests data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
-
Patent Agency Ranking
公开(公告)号：US12073121B2
公开(公告)日：2024-08-27
申请号：US18048292
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0631 , G06F3/0673
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
-
公开(公告)号：US20240134746A1
公开(公告)日：2024-04-25
申请号：US18048283
申请日：2022-10-19
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F11/10
CPC classification number: G06F11/108 , G06F11/106
Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
-
公开(公告)号：US11960754B2
公开(公告)日：2024-04-16
申请号：US17412830
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Revanth Kamaraj , Brian Toronyi , Balwinder Pal Sethi , Trapti Jain , Madhu , Chandrakanth Rapalli
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.
-
公开(公告)号：US20250021271A1
公开(公告)日：2025-01-16
申请号：US18782405
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
IPC: G06F3/06
Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
-
公开(公告)号：US20240235578A9
公开(公告)日：2024-07-11
申请号：US18048284
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Chandrakanth Rapalli , Yoav Weinberg , Tal Sharifie
CPC classification number: H03M13/095 , H03M13/611
Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.016 seconds)
