公开(公告)号：US12189596B2

公开(公告)日：2025-01-07

申请号：US18532552

申请日：2023-12-07

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F16/00 ,  G06F16/22

Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.

公开(公告)号：US20240193144A1

公开(公告)日：2024-06-13

申请号：US18532552

申请日：2023-12-07

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F16/22

CPC classification number: G06F16/2255

Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.

公开(公告)号：US12001678B2

公开(公告)日：2024-06-04

申请号：US17895696

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US12235764B2

公开(公告)日：2025-02-25

申请号：US17946960

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Steven R. Narum ,  Brian Toronyi

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/1027

Abstract: Apparatus and methods include receiving signaling indicative of performance of an operation to update a plurality of data entries written to a memory device and having a same offset from an initial physical address corresponding to each of the plurality of data entries and performing the operation to write the update to the plurality of data entries written to the memory device and having the same offset from the initial physical address corresponding to each of the plurality of data entries responsive to receiving the signaling indicative of performance of the operation to update the plurality of data entries.

公开(公告)号：US20240020223A1

公开(公告)日：2024-01-18

申请号：US17867375

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F12/02 ,  G06F9/50

CPC classification number: G06F12/023 ,  G06F9/5016 ,  G06F12/0292

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address of the memory resource nor a last physical address of the memory resource. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address of the memory resource. In contrast, in response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address of the memory resource.

公开(公告)号：US12259812B2

公开(公告)日：2025-03-25

申请号：US17867375

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F12/02 ,  G06F9/50

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.

公开(公告)号：US20240272811A1

公开(公告)日：2024-08-15

申请号：US18431743

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

Abstract: A plurality of data entries are written in a first memory bank that comprises a portion of a data structure that is stored across a plurality of memory banks. For a subsequent data entry, a determination is made that the subsequent data entry has a value that is greater than a first data entry among the plurality of data entries in the first memory bank and less than a second data entry among the plurality of data entries in the first memory bank. The subsequent data entry is written to an address location in a second memory bank of the plurality of memory banks that is between a lowermost address location and an uppermost address location of the second memory bank and a first bit corresponding to the address location in the second memory bank to which the subsequent data entry was written is stored in the data structure.

公开(公告)号：US20240069728A1

公开(公告)日：2024-02-29

申请号：US17895696

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Brian Toronyi ,  Scheheresade Virani

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0608 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/1009

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

公开(公告)号：US20240020036A1

公开(公告)日：2024-01-18

申请号：US17867396

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0683 ,  G06F3/0607

Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

公开(公告)号：US20220206707A1

公开(公告)日：2022-06-30

申请号：US17412830

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Revanth Kamaraj ,  Brian Toronyi ,  Balwinder Pal Sethi ,  Trapti Jain ,  Madhu ,  Chandrakanth Rapalli

IPC: G06F3/06

Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.