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公开(公告)号:US20240176748A1
公开(公告)日:2024-05-30
申请号:US18519871
申请日:2023-11-27
发明人: David A. Palmer
IPC分类号: G06F12/1009 , G06F12/0846
CPC分类号: G06F12/1009 , G06F12/0848
摘要: An apparatus can include a memory device and a controller coupled thereto. The controller can be configured to maintain a logical-to-physical (L2P) table including logical block addresses (LBAs). The LBAs are organized as partitions of the L2P table. Each partition of the L2P table includes a respective subset of the LBAs. The controller can be configured to monitor, for each partition of the LBA, a quantity of read/modify/write (R/M/W) operations and a quantity of read operations performed on the memory device at the respective subset of the LBAs. The controller can be configured to for each partition of the L2P table and based on the quantities of R/M/W operations and read operations performed on the memory device at the respective subset of the LBAs, adjust a value of respective granularities of the L2P table.
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公开(公告)号:US11454941B2
公开(公告)日:2022-09-27
申请号:US16510662
申请日:2019-07-12
发明人: Jonathan S. Parry , David A. Palmer
IPC分类号: G05B19/042 , H01L21/66 , G11C5/14
摘要: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each die of a plurality of dice in the power network, a first signal indicating that the respective die of the plurality of dice is in a high current state or a second signal indicating that the respective die of the plurality of dice is an active current state. The received signals include at least one second signal. The first die determines, based upon the received signals, a number of dice of the plurality of dice that are currently active and selects an activity threshold based upon that number. The first die further determines an activity level for the power network and transmits, to the plurality of dice, the first signal indicating that the first die is in the high current state in response to determining that the activity level is less than the activity threshold.
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公开(公告)号:US20220107886A1
公开(公告)日:2022-04-07
申请号:US17065455
申请日:2020-10-07
发明人: David A. Palmer
IPC分类号: G06F12/02 , G06F12/0873 , G06F12/1018 , G06F11/30
摘要: Methods, systems, and devices for multiple flash translation layers (FTLs) at a memory device are described to support two or more FTLs within a memory device. A first FTL may be configured to support data mapping using a defined granularity and a second FTL may be configured to support data mapping using a smaller granularity than the defined granularity or data that does not match the defined granularity, based on one or more characteristics of the data. A memory device may select between the FTLs to map data based on the one or more characteristics of the data and may write the data to the memory device. The memory device may store logical-to-physical mapping associated with the data, among other information, using the selected FTL.
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公开(公告)号:US20210303184A1
公开(公告)日:2021-09-30
申请号:US16830134
申请日:2020-03-25
发明人: David A. Palmer
摘要: A total power requirement for a plurality of memory operations is estimated. It is determined that the total power requirement would meet a power budget. In in response to determining that the total power requirement would meet the power budget, a power profile identifier associated with a first operation of the plurality of memory operations is adjusted. The first operation and the power profile identifier are issued to a memory device. The power profile identifier is used by the memory device to regulate an amount of power used when performing the first operation.
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公开(公告)号:US10761725B2
公开(公告)日:2020-09-01
申请号:US15906315
申请日:2018-02-27
发明人: David A. Palmer
IPC分类号: G06F3/06
摘要: The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure.
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公开(公告)号:US20190121730A1
公开(公告)日:2019-04-25
申请号:US16221846
申请日:2018-12-17
发明人: David A. Palmer
摘要: The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.
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公开(公告)号:US11422945B2
公开(公告)日:2022-08-23
申请号:US16831499
申请日:2020-03-26
发明人: David A. Palmer
IPC分类号: G06F12/1027
摘要: A method for managing memory addresses in a memory subsystem is described. The method includes determining that a chunk of logical addresses is sequentially written such that a set of physical addresses mapped to corresponding logical addresses in the chunk are sequential. Thereafter, the memory subsystem updates an entry in a sequential write table for the chunk to indicate that the chunk was sequentially written and a compressed logical-to-physical (L2P) table based on (1) the sequential write table and (2) a full L2P table. The full L2P table includes a set of full L2P entries and each entry corresponds to a logical address in the chunk and references a physical address in the set of physical addresses. The compressed L2P table includes an entry that references a first physical address of the first set of physical addresses that is also referenced by an entry in the L2P table.
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公开(公告)号:US20210233585A1
公开(公告)日:2021-07-29
申请号:US16776402
申请日:2020-01-29
发明人: Andrea Vigilante , David A. Palmer
摘要: Methods, systems, and devices for multichip memory packages are described. A multichip memory package may include at least two dies that include different types of memory, such as one die that includes non-volatile memory and another die that includes volatile memory. The package may include an in-package channel that supports internal data transfer between the two types of memory. For example, a respective controller for each of the types of memory may also be included in the package and may be coupled with each other via the in-package interface. In some cases, data may be read from one of the types of memory and written to the other type of memory in response to a single read or write command and without passing over any interface outside of the package.
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公开(公告)号:US20200285582A1
公开(公告)日:2020-09-10
申请号:US16296044
申请日:2019-03-07
发明人: David A. Palmer
IPC分类号: G06F12/0871 , G06F3/06 , G06F12/0868 , G11C5/04
摘要: A method for managing a readahead cache in a memory subsystem based on one or more active streams of read commands is described. The method includes receiving a read command that requests data from a memory component and determining whether the read command is part of an active stream of read commands based on a comparison of a set of addresses of the read command with one or more of (1) a command history table, which stores a set of command entries that each correspond to a received read command that has not been associated with an active stream, or (2) an active stream table, which stores a set of stream entries that each corresponds to active streams of read commands. The method further includes modifying a stream entry in the set of stream entries in response to determining that the read command is part of an active stream.
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公开(公告)号:US20180188965A1
公开(公告)日:2018-07-05
申请号:US15906315
申请日:2018-02-27
发明人: David A. Palmer
IPC分类号: G06F3/06
CPC分类号: G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G06F3/0688
摘要: The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure.
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